search for: drm_ioctl_nouveau_gem_cpu_fini

This patchset proposes to introduce a "staging" module option to dynamically enable features (mostly ioctls) that are merged but may be refined before they are declared "stable". The second patch illustrates the use of this staging option with the SET_TILING ioctl, which can be used to specify the tiling options of a PRIME-imported buffer. The staging parameter will allow us

Second version of this patchset addressing Ben's comments and fixing a few extra things. This patchset proposes to introduce a "staging" module option to dynamically enable features (mostly ioctls) that are merged but may be refined before they are declared "stable". The second patch illustrates the use of this staging option with the SET_TILING ioctl, which can be used to

...t;drm/drm.h> +#if defined(__cplusplus) +extern "C" { +#endif + #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) #define NOUVEAU_GEM_DOMAIN_GART (1 << 2) @@ -141,4 +145,8 @@ struct drm_nouveau_gem_cpu_fini { #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) +#if defined(__cplusplus) +} +#endif + #endif /* __NOUVEAU_DRM_H__ */ -- 2.6....

...11 >> +#define DRM_NOUVEAU_EXEC 0x12 >> #define DRM_NOUVEAU_GEM_NEW 0x40 >> #define DRM_NOUVEAU_GEM_PUSHBUF 0x41 >> #define DRM_NOUVEAU_GEM_CPU_PREP 0x42 >> @@ -197,6 +410,9 @@ struct drm_nouveau_svm_bind { >> #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) >> #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) >> >> +#define DRM_IOCTL_NOUVEAU_VM_INIT DRM_...

...DRM_NOUVEAU_EXEC?????????????? 0x12 >>> ? #define DRM_NOUVEAU_GEM_NEW??????????? 0x40 >>> ? #define DRM_NOUVEAU_GEM_PUSHBUF??????? 0x41 >>> ? #define DRM_NOUVEAU_GEM_CPU_PREP?????? 0x42 >>> @@ -197,6 +410,9 @@ struct drm_nouveau_svm_bind { >>> ? #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI?????? DRM_IOW >>> (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct >>> drm_nouveau_gem_cpu_fini) >>> ? #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + >>> DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) >>> ? +#define DRM_IOCTL_N...

...11 > +#define DRM_NOUVEAU_EXEC? ? ? ? ? ? ? ?0x12 > ?#define DRM_NOUVEAU_GEM_NEW? ? ? ? ? ? 0x40 > ?#define DRM_NOUVEAU_GEM_PUSHBUF? ? ? ? 0x41 > ?#define DRM_NOUVEAU_GEM_CPU_PREP? ? ? ?0x42 > @@ -197,6 +403,9 @@ struct drm_nouveau_svm_bind { > ?#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI? ? ? ?DRM_IOW > (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct > drm_nouveau_gem_cpu_fini) > ?#define DRM_IOCTL_NOUVEAU_GEM_INFO > ?DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct > drm_nouveau_gem_info) > > +#define DRM_IOCTL_...

...0x12 >>>> #define DRM_NOUVEAU_GEM_NEW 0x40 >>>> #define DRM_NOUVEAU_GEM_PUSHBUF 0x41 >>>> #define DRM_NOUVEAU_GEM_CPU_PREP 0x42 >>>> @@ -197,6 +410,9 @@ struct drm_nouveau_svm_bind { >>>> #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) >>>> #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) >>>> +#define DRM_IOCTL_NOUVEAU_VM_INIT...

...GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf) @@ -156,5 +158,6 @@ struct drm_nouveau_gem_cpu_fini { #define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep) #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) +#define DRM_IOCTL_NOUVEAU_GEM_SET_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOU...

...au_gem_new) > #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf) > #define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep) > #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) > #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) > +/* staging ioctls */ > > #endif /* __NOUVEAU_DRM_H__ */ > --...

From: Thierry Reding <treding at nvidia.com> This small series of patches implements support for waiting on and emitting fence FDs on kickoff. This enables explicit fencing and can be used for example to synchronize buffer accesses between the display engine and the GPU on Tegra. The first patch lays the groundwork by splitting up nouveau_fence_sync() to allow reuse. Patch 2 is where the

...DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new) > #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf) > @@ -149,5 +156,6 @@ struct drm_nouveau_gem_cpu_fini { > #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) > #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) > /* staging ioctls */ > +#define DRM_IOCTL_NOUVEAU_GEM_SET_TILING...

...EW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new) > #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf) > @@ -149,5 +156,6 @@ struct drm_nouveau_gem_cpu_fini { > #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) > #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) > /* staging ioctls */ > +#define DRM_IOCTL_NOUVEAU_GEM_SET_TILING...

Hi all, As some of you may know there some subtle distinction between C and C++ structs, thus one should wrap/annotate them roughly like below. ... #if defined(__cplusplus) extern "C" { #endif struct foo { int bar; ... }; ... #if defined(__cplusplus) } #endif In order to work around the lack of these users can wrap the header inclusion in the same way. For example:

From: Thierry Reding <treding at nvidia.com> Hi, This series implements a new IOCTL to submit push buffers that can optionally return a sync FD or sync object to userspace. This is useful in cases where userspace wants to synchronize operations between the GPU and another driver (such as KMS for display). Among other things this allows extensions such as eglDupNativeFenceFDANDROID to be

.... */ -#ifndef __NOUVEAU_DRM_H__ -#define __NOUVEAU_DRM_H__ +#ifndef _UAPI_DRM_NOUVEAU_DRM_H +#define _UAPI_DRM_NOUVEAU_DRM_H #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) @@ -135,4 +135,4 @@ struct drm_nouveau_gem_cpu_fini { #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) -#endif /* __NOUVEAU_DRM_H__ */ +#endif /* _UAPI_DRM_NOUVEAU_DRM_H */ diff --gi...

.... */ -#ifndef __NOUVEAU_DRM_H__ -#define __NOUVEAU_DRM_H__ +#ifndef _UAPI_DRM_NOUVEAU_DRM_H +#define _UAPI_DRM_NOUVEAU_DRM_H #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) @@ -135,4 +135,4 @@ struct drm_nouveau_gem_cpu_fini { #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) -#endif /* __NOUVEAU_DRM_H__ */ +#endif /* _UAPI_DRM_NOUVEAU_DRM_H */ diff --gi...

.... */ -#ifndef __NOUVEAU_DRM_H__ -#define __NOUVEAU_DRM_H__ +#ifndef _UAPI_DRM_NOUVEAU_DRM_H +#define _UAPI_DRM_NOUVEAU_DRM_H #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) @@ -135,4 +135,4 @@ struct drm_nouveau_gem_cpu_fini { #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini) #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info) -#endif /* __NOUVEAU_DRM_H__ */ +#endif /* _UAPI_DRM_NOUVEAU_DRM_H */ diff --gi...

Hi guys, I'd like to start a new thread about explicit fence synchronization. This time with a Nouveau twist. :-) First, let me define what I understand by implicit/explicit sync: Implicit synchronization * Fences are attached to buffers * Kernel manages fences automatically based on buffer read/write access Explicit synchronization * Fences are passed around independently * Kernel takes

Hi there, Resending these now that they've had some more polish and testing, and I heard that Ben's vacation is over :-) These patches work as a starting point for more explicit error mechanisms and better robustness. At the moment, when a job hangs or faults, it seems that nouveau doesn't quite know how to handle the situation and often results in a hang. Some of these situations