search for: driconfig

...asks to the client > in the case of GLX. So whatever 10 bit format comes first will win when > building the assignment to GLXFBConfigs. > > I looked at the code and how it behaves. In practice Intel gfx works because > it's a classic DRI driver with its own method of building the DRIconfig's, > and it only exposes the BGR101010 formats, so no danger of mixups. AMD's > gallium drivers expose both BGR and RGB ordered 10 bit formats, but due to > the ordering, the matching ends up only assigning the desired BGR formats > that are good for AMD hw, discarding the RGB f...

...gt;> in the case of GLX. So whatever 10 bit format comes first will win when >> building the assignment to GLXFBConfigs. >> >> I looked at the code and how it behaves. In practice Intel gfx works because >> it's a classic DRI driver with its own method of building the DRIconfig's, >> and it only exposes the BGR101010 formats, so no danger of mixups. AMD's >> gallium drivers expose both BGR and RGB ordered 10 bit formats, but due to >> the ordering, the matching ends up only assigning the desired BGR formats >> that are good for AMD hw, disc...

...ven transmit those masks to the client in the case of GLX. So whatever 10 bit format comes first will win when building the assignment to GLXFBConfigs. I looked at the code and how it behaves. In practice Intel gfx works because it's a classic DRI driver with its own method of building the DRIconfig's, and it only exposes the BGR101010 formats, so no danger of mixups. AMD's gallium drivers expose both BGR and RGB ordered 10 bit formats, but due to the ordering, the matching ends up only assigning the desired BGR formats that are good for AMD hw, discarding the RGB formats. nouveau...

In case anyone's curious about 30bpp framebuffer support, here's the current status: Kernel: Ben and I have switched the code to using a 256-based LUT for Kepler+, and I've also written a patch to cause the addfb ioctl to use the proper format. You can pick this up at: https://github.com/skeggsb/linux/commits/linux-4.16 (note the branch!)

...left out. > > > On 03/05/2018 01:40 PM, Ilia Mirkin wrote: >> >> On Mon, Mar 5, 2018 at 2:25 AM, Mario Kleiner >> <mario.kleiner.de at gmail.com> wrote: >>> Afaics EGL does the right thing wrt. channelmask matching of EGLConfigs >>> to >>> DRIconfigs, so we could probably implement dri_loader_get_cap(screen, >>> DRI_LOADER_CAP_RGBA_ORDERING) == TRUE for the EGL loaders. >>> >>> But for GLX it is not so easy or quick. I looked if i could make the >>> servers >>> GLX send proper channelmask attributes...