search for: dram

After update from centos 6.6 to centos 6.7 and reboot it, I have get a lot of this error into /var/log/messages: > May??3 11:27:20 s-virt kernel: EDAC MC0: CE row 2, channel 1, label > "": (Branch=0 DRAM-Bank=2 RDWR=Read RAS=6093 CAS=896, CE Err=0x10000 > (Correctable Patrol Data ECC)) > May??3 11:27:21 s-virt kernel: EDAC MC0: CE row 2, channel 1, label > "": (Branch=0 DRAM-Bank=1 RDWR=Read RAS=1330 CAS=4, CE Err=0x2000 > (Correctable Non-Mirrored Demand Data ECC)) > May??...

...nd hypervisor logs for both the good and bad cases > (ideally with the same kernel version use in both runs, so that we > can exclude kernel behavior differences). Here are some dmesg excerpts, all performed with Linux 4.1.3. When booting with Xen 4.1.4: AMD64 EDAC driver v3.4.0 EDAC amd64: DRAM ECC enabled. EDAC amd64: F10h detected (node 0). EDAC MC: DCT0 chip selects: EDAC amd64: MC: 0: 0MB 1: 0MB EDAC amd64: MC: 2: 2048MB 3: 2048MB EDAC amd64: MC: 4: 0MB 5: 0MB EDAC amd64: MC: 6: 0MB 7: 0MB EDAC MC: DCT1 chip selects: EDAC amd64: MC: 0: 0MB 1: 0MB EDAC...

I haven't yet done as much experimentation as Andreas Pflug has, but I can confirm I'm also running into this bug with Xen 4.4.1. I've only tried Linux kernel 3.16.43, but as Dom0: EDAC MC: Ver: 3.0.0 AMD64 EDAC driver v3.4.0 EDAC amd64: DRAM ECC enabled. EDAC amd64: NB MCE bank disabled, set MSR 0x0000017b[4] on node 0 to enable. EDAC amd64: ECC disabled in the BIOS or no ECC capability, module will not load. AMD64 EDAC driver v3.4.0 EDAC amd64: DRAM ECC enabled. EDAC amd64: NB MCE bank disabled, set MSR 0x0000017b[4] on node 0 to enab...

...ernel 2.6.18-128.7.1.el5xen" to "kernel 2.6.18-164.el5xen" After rebooting, my message log is flooded every second or so with this error messages: Oct 6 14:52:20 xenserver1 kernel: EDAC MC0: UE row 0, channel-a= 0 channel-b= 1 labels "-": NON-FATAL recoverable (Branch=0 DRAM-Bank=0 Buffer ID = 0 RDWR=Read RAS=0 CAS=0 NON-FATAL recovera ble Err=0x2000 (FB-DIMM Configuration Write error on first attempt)) and Oct 6 15:17:23 xenserver1 kernel: EDAC MC0: CE row 0, channel 0, label "": Corrected error (Branch=0 DRAM-Bank=0 RDWR=Read RAS=0 CAS=0, CE Err=0x10000...

...ern drives. Bringing platters over 1000 times deep into hysteresis back and forth is enough to destroy even residual magnetization related to magnetic domain aging... On modern drives though... No, I decided to not spoil it for those who decides to read that article. One thing I learned from there: DRAM had more persistent imprint of information that was sitting in it, which appears much harder to destroy than information on hard drive. I hope I intrigued you enough to go and read that article. Valeri ++++++++++++++++++++++++++++++++++++++++ Valeri Galtsev Sr System Administrator Department of...

...the initial values of the parameters those obtained from the nls fit. Is a problem of the initial estimates of the parameters that I get the error or could be something else? The code for the nls fit was: options(contrasts=c("contr.helmert","contr.poly")) VA1.lis<-nlsList(DRAM~SSlogis(MED,phi1,phi2,phi3)|TRAT, data=VA1,na.action=na.omit) The code for the gnls fit was (using a 'difference parameterization' like SAS): options(contrasts=c("contr.SAS","contr.poly")) VA1.gnls<-gnls(DRAM~SSlogis(MED,phi1,phi2,phi3), data=VA1,params=list(phi1~T...

...gt; See http://llvm.org/bugs/show_bug.cgi?id=6210. Chris is correct at the coarse granularity, but there are some trades to be made at the fine. There is some interesting work from MIT in the context of image processing kernels related to the relative costs of saving intermediates out to cache or DRAM vs recomputing them - often recomputing takes one to two orders of magnitude less power. The tile hashing mechanism in recent MALI GPUs is designed to address the same problem: accesses to memory - especially off-chip memory - use a surprisingly large amount of power. Optimising for this requir...

Initially reported to debian (http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=810964), redirected here: With AMD Opteron 6xxx processors, half of the memory controllers are missing from /sys/devices/system/edac/mc Checked with single 6120 (dual memory controller) and twin 6344 (2x dual MC), other dual-module CPUs might be affected too. Booting plain Linux (3.2, 3.16, 4.1, 4.3), all memory

...as much experimentation as Andreas Pflug has, but I > > can confirm I'm also running into this bug with Xen 4.4.1. > > > > I've only tried Linux kernel 3.16.43, but as Dom0: > > > > EDAC MC: Ver: 3.0.0 > > AMD64 EDAC driver v3.4.0 > > EDAC amd64: DRAM ECC enabled. > > EDAC amd64: NB MCE bank disabled, set MSR 0x0000017b[4] on node 0 to enable. > > EDAC amd64: ECC disabled in the BIOS or no ECC capability, module will not > > load. > > AMD64 EDAC driver v3.4.0 > > EDAC amd64: DRAM ECC enabled. > > EDAC amd64:...

Hello list, while following this list for more then 1 year, I feel that this list was a great way to get insights into ZFS. Thank you all for contributing. Over the last month''s I was writing a little "whitepaper" trying to consolidate the knowledge collected here. It has now reached a "beta" state and I would like to share the result with you. I call it -

...apply to all recent big intel cores), it won't contend with other cores for the L3 cache. So misses here are where cores start to feel each other's presence. https://reviews.llvm.org/P7943 --event=LLC-load-misses These are misses in last level cache (LLC). I.e. times that we have to go to DRAM (SLOOOW). The getVA codepath show up strongly and we see the memcpy into the output. We may want to consider a nontemporal memcpy to at least avoid polluting the cache. These misses contend on the DRAM bus (although currently it may be underutilized and so adding more parallelism will help to keep...

Hi, Just got some of the new Soekris 1401 VPN cards based on the hifn 7955 chip. hifn0 mem 0xe8510000-0xe8517fff,0xe8518000-0xe8519fff,0xe851a000-0xe851afff irq 5 at device 0.0 on pci1 hifn0: Hifn 7955, rev 0, 32KB dram, 64 sessions vs hifn0 mem 0xeb902000-0xeb902fff,0xeb901000-0xeb901fff irq 10 at device 8.0 on pci0 hifn0: Hifn 7951, rev 0, 128KB sram, 193 sessions When it says "n sessions" how does that specifically impact IPSEC ? Does it really mean I can only have 64 SAs ? ---Mike -----------...

...s going on? You mean you used your bsd-ports-provided gcc to compile LLVM and you've got 4 times a bus-error during the build? In this case, it cannot be a LLVM problem. In the linux-community, people say that bus-error's are almost always because of faulty hardware, e.g. problem with DRAM timing, overheated CPU, power-supply that cannot provide enought power during current surges, things like that.

...t; On Tue, Aug 13, 2019 at 06:36:33PM -0700, Dan Williams wrote: > > > Section alignment constraints somewhat save us here. The only example > > > I can think of a PMD not containing a uniform pgmap association for > > > each pte is the case when the pgmap overlaps normal dram, i.e. shares > > > the same 'struct memory_section' for a given span. Otherwise, distinct > > > pgmaps arrange to manage their own exclusive sections (and now > > > subsections as of v5.3). Otherwise the implementation could not > > > guarantee different...

On Tue, Jun 17, 2008 at 4:56 PM, Edd Barrett <vext01 at gmail.com> wrote: > On Tue, Jun 17, 2008 at 4:51 PM, Edd Barrett <vext01 at gmail.com> wrote: >> I am trying the same with gcc-4.2 now. > > The above results were infact with gcc-4.2. My apologies. With 3.3.5 my first test took 5 times to produce a non "bus error" build. There were no 'make

...D-8131 PCI-X IOAPIC (rev 01) 00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration 00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map 00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control 00:19.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration 00:19.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address...

Hello everyone! Could you tell me if FreeBSD supports memory page nulling when releasing it to prevent unauthorized access to data left in the page after it's allocated again. If it does, what sys calls etc provide that? IMHO this is an important issue when operating data with different sensivity levels. Thanks in advance. Nick

Hi all, (down to the wire here on EDU grant pricing :) i''m looking at buying a pair of 7110''s in the EDU grant sale. The price is sure right. I''d use them in a mirrored, cold-failover config. I''d primarily be using them to serve a vmware cluster; the current config is two standalone ESX servers with local storage, 450G of SAS RAID10 each. the 7110 price

...AC97 Audio Controller (rev 60) 00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration 00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map 00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control 00:19.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration 00:19.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Ma...

On Tue, Aug 13, 2019 at 06:36:33PM -0700, Dan Williams wrote: > Section alignment constraints somewhat save us here. The only example > I can think of a PMD not containing a uniform pgmap association for > each pte is the case when the pgmap overlaps normal dram, i.e. shares > the same 'struct memory_section' for a given span. Otherwise, distinct > pgmaps arrange to manage their own exclusive sections (and now > subsections as of v5.3). Otherwise the implementation could not > guarantee different mapping lifetimes. > > That said,...