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From: Jim Grosbach [mailto:grosbach at apple.com] Sent: Friday, October 25, 2013 4:31 PM To: David Peixotto Cc: Renato Golin; LLVM Dev Subject: Re: [LLVMdev] Add support for ldr pseudo instruction in ARM integrated assembler On Oct 25, 2013, at 3:53 PM, David Peixotto <dpeixott at codeaurora.org> wrote: Hi Renato, Thanks for the thoughtful reply. Please find my thoughts below. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation From: Renato Golin [ <mailto:renato.golin at linaro.org> mailto:renato.g...

On Oct 25, 2013, at 6:14 PM, David Peixotto <dpeixott at codeaurora.org> wrote: > From: Jim Grosbach [mailto:grosbach at apple.com] > Sent: Friday, October 25, 2013 4:31 PM > To: David Peixotto > Cc: Renato Golin; LLVM Dev > Subject: Re: [LLVMdev] Add support for ldr pseudo instruction in ARM integrated assembler > > >...

"David Peixotto" <dpeixott at codeaurora.org> writes: > I think the main benefit of a scheme like this would be that a pull > request tells a code owner which patches require their attention. As a > contributor it would be nice to see your patch in a queue somewhere > rather than just be buried down the maili...

On Oct 25, 2013, at 3:53 PM, David Peixotto <dpeixott at codeaurora.org> wrote: > Hi Renato, Thanks for the thoughtful reply. Please find my thoughts below. > > -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation > > > From: Renato Golin [mailto:renato.golin at linaro.org] &...

"David Peixotto" <dpeixott at codeaurora.org> writes: > I'd like to build llvm with assertions enabled, but build clang with > assertions disabled. In other words, I'd like lvm in Release+Asserts mode, > but clang in Release mode. > > Is it possible to do this with one top level configure/make comm...

...golin at linaro.org] Sent: Friday, October 25, 2013 1:11 PM To: David Peixotto Cc: LLVM Dev; Logan Chien; Gabor Ballabas; Rafael Espíndola; Richard Barton; Amara Emerson Subject: Re: Add support for ldr pseudo instruction in ARM integrated assembler On 25 October 2013 18:33, David Peixotto <dpeixott at codeaurora.org> wrote: Both armasm and gnu as support an ldr pseudo instruction for loading constants that lowers to either a mov, movn, or a pc-relative ldr from the constant pool. It would be great if the llvm integrated assembler could support this feature as well. Hi David, As mu...

Hi, I'd like to build llvm with assertions enabled, but build clang with assertions disabled. In other words, I'd like lvm in Release+Asserts mode, but clang in Release mode. Is it possible to do this with one top level configure/make command? If not, any idea how much work would it be to add this feature to llvm? I'm not very familiar with llvm's build system. Thanks!

Both armasm and gnu as support an ldr pseudo instruction for loading constants that lowers to either a mov, movn, or a pc-relative ldr from the constant pool. It would be great if the llvm integrated assembler could support this feature as well. For example, using gnu as to compile this code: .text foo: ldr r0, =0x1 ldr r0, =-0x1 ldr r0, =0x1000001 ldr r0, =bar

On Sep 6, 2012, at 4:40 PM, David Peixotto <dpeixott at codeaurora.org> wrote: > -----Original Message----- > From: Bob Wilson [mailto:bob.wilson at apple.com] > Sent: Thursday, September 06, 2012 3:39 PM > To: David Peixotto > Cc: 'Peter Couperus'; 'Jim Grosbach'; 'Jakob Olesen'; llvmdev at cs.uiuc.edu &gt...

I think the main benefit of a scheme like this would be that a pull request tells a code owner which patches require their attention. As a contributor it would be nice to see your patch in a queue somewhere rather than just be buried down the mailing list. When patches are sent to llvm-commits it can be hard to tell if a code owner has noticed the patch because it is a very high-volume list.

On 25 October 2013 18:33, David Peixotto <dpeixott at codeaurora.org> wrote: > Both armasm and gnu as support an ldr pseudo instruction for loading > constants that lowers to either a mov, movn, or a pc-relative ldr from the > constant pool. It would be great if the llvm integrated assembler could > support this feature as well. &gt...

...day, September 07, 2012 10:57 AM > To: David Peixotto > Cc: 'Peter Couperus'; 'Jim Grosbach'; 'Jakob Olesen'; llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] Unaligned vector memory access for ARM/NEON. > > > On Sep 6, 2012, at 4:40 PM, David Peixotto <dpeixott at codeaurora.org> > wrote: > > > -----Original Message----- > > From: Bob Wilson [mailto:bob.wilson at apple.com] > > Sent: Thursday, September 06, 2012 3:39 PM > > To: David Peixotto > > Cc: 'Peter Couperus'; 'Jim Grosbach'; 'Jakob Olese...

On Nov 1, 2013, at 12:06 PM, David Peixotto <dpeixott at codeaurora.org> wrote: >>> I was thinking that without the .ltorg directive the constant pool >>> would go at the end of the section. >>> >> So where does the assembler place the constant pool(s) if that directive >> isn't present? I was under the...

On Nov 1, 2013, at 12:15 PM, David Peixotto <dpeixott at codeaurora.org> wrote: >>>>> I was thinking that without the .ltorg directive the constant pool >>>>> would go at the end of the section. >>>>> >>>> So where does the assembler place the constant pool(s) if that >>>> direc...

On Sep 6, 2012, at 2:48 PM, David Peixotto <dpeixott at codeaurora.org> wrote: > Hi Pete, > > We ran into the same issue with generating vector loads/stores for vectors > with less than word alignment. It seems we took a similar approach to > solving the problem by modifying the logic in allowsUnalignedMemoryAccesses. > > A...

> > I was thinking that without the .ltorg directive the constant pool > > would go at the end of the section. > > > So where does the assembler place the constant pool(s) if that directive > isn't present? I was under the impression it was always required. >From my understanding it is not required. I see that GCC will place it at the end of the section. I don't

I have some assembly code that uses .equ to set a symbol to a computed constant. It works in GCC but not LLVM. I am not sure about the correct terminology, but here is an example: .syntax unified .set size, end - start add r0, r0, #size start: .space 0x10 end: GCC will compile this to `add r0, r0, #16`. Compiling with llvm-mc gives: set.s:4:13: error: invalid operand for

...lson at apple.com] Sent: Thursday, September 06, 2012 3:39 PM To: David Peixotto Cc: 'Peter Couperus'; 'Jim Grosbach'; 'Jakob Olesen'; llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] Unaligned vector memory access for ARM/NEON. On Sep 6, 2012, at 2:48 PM, David Peixotto <dpeixott at codeaurora.org> wrote: > Hi Pete, > > We ran into the same issue with generating vector loads/stores for > vectors with less than word alignment. It seems we took a similar > approach to solving the problem by modifying the logic in allowsUnalignedMemoryAccesses. > >...

2) For lag in execution time due to floating point operations, it was clearly observed that gcc used floating point instruction FSQRT, where as clang seemed to use emulated function (?) BL SQRT. Note that we used the following flags for both clang as well as gcc compilation. -march=armv7-a -mfloat-abi=softfp -mfpu=vfpv3-d16 -mtune=cortex-a8 Infact, i was surprised to see that even when

Matheus, The ARM backend reports these kinds of errors using FatalError method of MCContext. You can see some examples in ARMAsmBackend.cpp (search for "out of range pc-relative fixup value"). -David From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Matheus Almeida Sent: Tuesday, December 03, 2013 5:37 AM To: llvmdev at cs.uiuc.edu