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Hi, We are now about halfway between the 3.4 and 3.5 releases, and I would like to start preparing for a 3.4.1 release. Here is my proposed release schedule: Mar 26 - April 9: Identify and backport additional bug fixes to the 3.4 branch. April 9 - April 18: Testing Phase April 18: 3.4.1 Release How you can help: - If you have any bug fixes you think should be included to 3.4.1, send me an

...r name than {d1, d2}. LLVM models the sequence constraint as a single super-register, so we define pseudo-registers D1_D2, D3_D4, … in addition to the existing Q0, Q1, … From the register allocator's point of view, the vld1.64 instruction has two operands: a GPR operands for the address, and a DPair operand representing the two consecutive d-registers. This model makes it easy to handle register sequence constraints, and we don't have to worry about what ISA designers decide to call a 'register'. The cost is a fairly high number of pseudo-registers that the ISA didn't dare to...

...legal: All 8-bit types via ldrb/strb to GPR. (i8, v1i8, v2i4, v4i2, v8i1) All 16-bit types via ldrh/strh to GPR. (i16, f16, v1i16, v2i8, ...) All 32-bit types via ldr/str to GPR and vldr/vstr to SPR. All 64-bit types via ldrd/strd to GPRPair and vldr/vstr to DPR. All 128-bit types via vld1/vst1 to DPair. All 192-bit types via vld1/vst1 to DTriple. All 256-bit types via vld1/vst1 to DQuad. This larger set of legal types also makes it easier to handle things like extractelement <8 x i8> which currently produces an illegal type and is thus obfuscated by the type legalizer. An i8 live range cou...