search for: dp_downstreamport_present

...-423,6 +423,52 @@ bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux, } EXPORT_SYMBOL(drm_dp_send_real_edid_checksum); +static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK; + + if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4) + port_count = 4; + + return port_count; +} + +/** + * drm_dp_downstream_read_info() - read DPCD downstream port info if available + * @aux: DisplayPort AUX channel + * @dpcd: A cached copy of the port's DPCD + * @downstream_p...

...-423,6 +423,56 @@ bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux, } EXPORT_SYMBOL(drm_dp_send_real_edid_checksum); +static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK; + + if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4) + port_count = 4; + + return port_count; +} + +/** + * drm_dp_read_downstream_info() - read DPCD downstream port info if available + * @aux: DisplayPort AUX channel + * @dpcd: A cached copy of the port's DPCD + * @downstream_p...

...tream_ports[DP_MAX_DOWNSTREAM_PORTS]) > +{ > + int ret; > + u8 len; > + > + memset(downstream_ports, 0, DP_MAX_DOWNSTREAM_PORTS); > + > + /* No downstream info to read */ > + if (!drm_dp_is_branch(dpcd) || > + dpcd[DP_DPCD_REV] < DP_DPCD_REV_10 || > + !(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) > + return 0; > + > + len = (dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK) * 4; I'm having a hard time rationalizing DP_MAX_DOWNSTREAM_PORTS being 16, but only having 4 ports worth of data in the DP_DOWNSTREAM_PORT_* registers. Do you kno...

...const u8 dpcd[DP_RECEIVER_CAP_SIZE], + u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]) +{ + int ret; + u8 len; + + memset(downstream_ports, 0, DP_MAX_DOWNSTREAM_PORTS); + + /* No downstream info to read */ + if (!drm_dp_is_branch(dpcd) || + dpcd[DP_DPCD_REV] < DP_DPCD_REV_10 || + !(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) + return 0; + + len = (dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK) * 4; + ret = drm_dp_dpcd_read(aux, DP_DOWNSTREAM_PORT_0, downstream_ports, + len); + + return ret == len ? 0 : -EIO; +} +EXPORT_SYMBOL(drm_dp_downstream_read_info); + /**...

...ector, + const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const struct drm_dp_desc *desc) +{ + /* Some eDP panels don't set a valid value for the sink count */ + return connector->connector_type != DRM_MODE_CONNECTOR_eDP && + dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 && + dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT && + !drm_dp_has_quirk(desc, 0, DP_DPCD_QUIRK_NO_SINK_COUNT); +} +EXPORT_SYMBOL(drm_dp_has_sink_count); + /* * I2C-over-AUX implementation */ diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 984e49194c...

...8 len; > > > + > > > + memset(downstream_ports, 0, DP_MAX_DOWNSTREAM_PORTS); > > > + > > > + /* No downstream info to read */ > > > + if (!drm_dp_is_branch(dpcd) || > > > + dpcd[DP_DPCD_REV] < DP_DPCD_REV_10 || > > > + !(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) > > > + return 0; > > > + > > > + len = (dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK) * 4; > > > > I'm having a hard time rationalizing DP_MAX_DOWNSTREAM_PORTS being 16, but > > only > > having 4...

...> > + int ret; > > + u8 len; > > + > > + memset(downstream_ports, 0, DP_MAX_DOWNSTREAM_PORTS); > > + > > + /* No downstream info to read */ > > + if (!drm_dp_is_branch(dpcd) || > > + dpcd[DP_DPCD_REV] < DP_DPCD_REV_10 || > > + !(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) > > + return 0; > > + > > + len = (dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK) * 4; > > I'm having a hard time rationalizing DP_MAX_DOWNSTREAM_PORTS being 16, but > only > having 4 ports worth of data in the DP_DOWN...

...gt; > > + memset(downstream_ports, 0, DP_MAX_DOWNSTREAM_PORTS); > > > > + > > > > + /* No downstream info to read */ > > > > + if (!drm_dp_is_branch(dpcd) || > > > > + dpcd[DP_DPCD_REV] < DP_DPCD_REV_10 || > > > > + !(dpcd[DP_DOWNSTREAMPORT_PRESENT] & > > > > DP_DWN_STRM_PORT_PRESENT)) > > > > + return 0; > > > > + > > > > + len = (dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK) * > > > > 4; > > > > > > I'm having a hard time rationalizing DP_MAX...

To start off: this patch series is less work to review then it looks - most (but not all) of the nouveau related work has already been reviewed elsewhere. Most of the reason I'm asking for an RFC here is because this code pulls a lot of code out of i915 and into shared DP helpers. Anyway-nouveau's HPD related code has been collecting dust for a while. Other then the occasional runtime PM

Most of the reason I'm asking for an RFC here is because this code pulls a lot of code out of i915 and into shared DP helpers. Anyway-nouveau's HPD related code has been collecting dust for a while. Other then the occasional runtime PM related and MST related fixes, we're missing a lot of nice things that have been added to DRM since this was originally written. Additionally, the code

Most of the reason I'm asking for an RFC here is because this code pulls a lot of code out of i915 and into shared DP helpers. Anyway-nouveau's HPD related code has been collecting dust for a while. Other then the occasional runtime PM related and MST related fixes, we're missing a lot of nice things that have been added to DRM since this was originally written. Additionally, the code

To start off: this patch series is less work to review then it looks - most (but not all) of the nouveau related work has already been reviewed elsewhere. Most of the reason I'm asking for an RFC here is because this code pulls a lot of code out of i915 and into shared DP helpers. Anyway-nouveau's HPD related code has been collecting dust for a while. Other then the occasional runtime PM