search for: dp4

...arate physical register? > > Evan > I don't think so. There are 4x4x4x4 = 256 permutations. For example: * xyzw: default * zxyw * yyyy: splat Even if can model each of these 256 cases as a separate physical register, how can I model the use of r0.xyzw in the following example: // dp4 = dot product 4-element dp4 r0.x, r1, r2 dp4 r0.y, r3, r4 dp4 r0.z, r5, r6 dp4 r0.w, r7, r8 sub r5, r0.xyzw, r6 -- View this message in context: http://www.nabble.com/Modeling-GPU-vector-registers%2C-again-%28with-my-implementation%29-tp22001613p22034856.html Sent from the LLVM - Dev mailing lis...

...de with an extra integer constant per register that would encode the swizzle mask in 32bits. The correct swizzles can then be generated in the asm printer by decoding the integer constant. This does require having extra moves, but your example below would end up being something like the following: dp4 r100, r1, r2 mov r0.x, r100 (float4 => float1 extract_vector_elt) dp4 r101, r4, r5 mov r3.x, r101 (float4 => float1 extract_vector_elt) iadd r6.xy__, r0.x000, r3.0x00(float1 + float1 => float2 build_vector) dp4 r7.x, r8, r9 <as above> dp4 r10.x, r11, r12 <as above> iadd r13.xy_...

I've tweaked Tim Wood's Mac OS X DP4 patches so they compile and run reasonably well on OS X DP4 and added a couple minor tweaks of my own. I've placed diffs from the head revision in cvs at my web site: <http://www.gizzywump.com/vorbis-macosx-diffs> This includes a new file at vorbis-tools/libao/ao_macosx.c, which is in t...

On Feb 13, 2009, at 9:47 AM, Alex wrote: > It seems to me that LLVM sub-register is not for the following > hardware architecture. > > All instructions of a hardware are vector instructions. All > registers contains > 4 32-bit FP sub-registers. They are called r0.x, r0.y, r0.z, r0.w. > > Most instructions write more than one elements in this way: > > mul

It seems to me that LLVM sub-register is not for the following hardware architecture. All instructions of a hardware are vector instructions. All registers contains 4 32-bit FP sub-registers. They are called r0.x, r0.y, r0.z, r0.w. Most instructions write more than one elements in this way: mul r0.xyw, r1, r2 add r0.z, r3, r4 sub r5, r0, r1 Notice that the four elements of r0 are written

I'm going to want to submit patches for MacOS X in the near future (hopefully tonight or tomorrow night), but I don't see what flags to cvs diff you guys like to receive. Included in these patches will be a MacOS X module for libao which uses the CoreAudio framework along with some other minor stuff. -tim --- >8 ---- List archives: http://www.xiph.org/archives/ Ogg project

...irect3D shaders from our hardware, I have a program which translates the Direct3D shader assembly to LLVM assembly. I added several intrinsics for this purpose. It's a vector ISA and has some special instructions like: * rcp (reciprocal) * frc (the fractional portion of each input component) * dp4 (dot product) * exp (exponential) * max, min These operations are very specific to 3D graphics and missing from the LLVM instructions. The vector LLVM extension is not enough to compiled Direct3D shaders. The result LLVM assembly is assembled by llvm-as, and directly passed to llc. The frontend is...

http://bugs.freedesktop.org/show_bug.cgi?id=27136 Summary: blank screen with G98 [Quadro NVS 420] (NV98) dual GPU, 4-head Product: xorg Version: 7.5 Platform: x86-64 (AMD64) OS/Version: Linux (All) Status: NEW Severity: normal Priority: medium Component: Driver/nouveau

I can open all programs that use WINE, with Lion DP4

...ware, > I have a program which translates the Direct3D shader assembly to LLVM > assembly. I added several intrinsics for this purpose. > It's a vector ISA and has some special instructions like: > * rcp (reciprocal) > * frc (the fractional portion of each input component) > * dp4 (dot product) > * exp (exponential) > * max, min > These operations are very specific to 3D graphics and missing from the > LLVM instructions. The vector LLVM extension is not enough to compiled > Direct3D shaders. ok. > The result LLVM assembly is assembled by llvm-as, and dire...

...400x1050 59.98 1280x1024 60.02 1440x900 59.89 1280x960 60.00 1360x768 59.80 59.96 1152x864 60.00 1024x768 60.00 800x600 60.32 56.25 640x480 59.94 VGA1 disconnected (normal left inverted right x axis y axis) DP4 disconnected (normal left inverted right x axis y axis) HDMI1 disconnected (normal left inverted right x axis y axis) Step 2: $ xrandr --listproviders Providers: number : 2 Provider 0: id: 0x8d cap: 0xb, Source Output, Sink Output, Sink Offload crtcs: 3 outputs: 4 associated providers: 0 name:Inte...

...mypalette$confidence="#FF9966" mypalette$limits="#FF0000" mypalette$major="#000000" mypalette$minor="#cccccc" mypalette$actual="#aaaaaa" mypalette$dp1="#9900FF" mypalette$dp2="#EEEE00" mypalette$dp3="#CCFF00" mypalette$dp4="#00CCFF" mypalette$dp5="#FF00CC" #Raw Data channel1 <- odbcConnectExcel(SOURCEDATA) sqlTables(channel1) sh1 <- sqlFetch(channel1, "Actuals$") close(channel1) channel2 <- odbcConnectExcel(REGRESSORS) sqlTables(channel2) sh2 <- sqlFetch(channel2, "data...

...effect variables. d3d10: Implement ID3D10Effect::GetVariableByName(). wined3d: Recognize SM4 arrays. wined3d: Recognize the SM4 constant buffer register type. wined3d: Recognize the SM4 rsq opcode. wined3d: Recognize the SM4 dp3 opcode. wined3d: Recognize the SM4 dp4 opcode. wined3d: Rename _WineD3D_GL_Info to struct wined3d_gl_info. wined3d: Store a pointer to wined3d_gl_info in struct WineD3DContext. wined3d: Pass the context instead of the device to the various context functions. wined3d: Always use context_bind_fbo() to change the fr...

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