Displaying 1 result from an estimated 1 matches for "dmiuemsk".
2013 Aug 20
0
Xen Security Advisory 59 (CVE-2013-3495) - Intel VT-d Interrupt Remapping engines can be evaded by native NMI interrupts
...e Host Bridge. This is
applicable to all chipsets.
Alternatively hypervisor or Dom0 can block SERR error signaling due to
Unsupported Request error resulting from malformed MSI requests by setting bit
20 ("Unsupported Request Error Mask") in memory configuration register at
offset 0x1C8 (DMIUEMSK) in Root Complex Register Range. The base address of
Root Complex Register Range is defined by DMIBAR register (offset 0x68) in PCI
configuration space of the Host Bridge (BDF 00:00.0). For this alternative,
less intrusive workaround it was so far not determined whether it is applicable
to all or j...