Displaying 20 results from an estimated 29 matches for "dmaobj".
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db_obj
2014 Dec 22
2
3.19.0-rc1 nouvea build failure on GeForce GT 610 only
CHK kernel/config_data.h
CC [M] drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.o
drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c: In function
‘nvd0_dmaobj_bind’:
drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c:54:8: error:
‘GM204_DISP_CORE_CHANNEL_DMA’ undeclared (first use in this function)
case GM204_DISP_CORE_CHANNEL_DMA:
^
drivers/gpu/drm/nouveau/c...
2016 Dec 20
1
[PATCH] drm/nouveau/dma: use rb_entry()
...55d17 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c
@@ -34,7 +34,7 @@ nvkm_dma_search(struct nvkm_dma *dma, struct nvkm_client *client, u64 object)
struct rb_node *node = client->dmaroot.rb_node;
while (node) {
struct nvkm_dmaobj *dmaobj =
- container_of(node, typeof(*dmaobj), rb);
+ rb_entry(node, typeof(*dmaobj), rb);
if (object < dmaobj->handle)
node = node->rb_left;
else
@@ -67,7 +67,7 @@ nvkm_dma_oclass_new(struct nvkm_device *device,
dmaobj->handle = oclass->object;
while (*ptr) {
-...
2014 Dec 22
1
3.19.0-rc1 nouvea build failure on GeForce GT 610 only
On Mon, 2014-12-22 at 14:37 +0100, Paul Bolle wrote:
> On Mon, 2014-12-22 at 13:01 +0000, Sid Boyce wrote:
> > CHK kernel/config_data.h
> > CC [M] drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.o
> > drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c: In function
> > ‘nvd0_dmaobj_bind’:
> > drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c:54:8: error:
> > ‘GM204_DISP_CORE_CHANNEL_DMA’ undeclared (first use in this function)
> > case GM204_DISP_CORE...
2014 Dec 22
0
3.19.0-rc1 nouvea build failure on GeForce GT 610 only
Hi Sid,
On Mon, 2014-12-22 at 13:01 +0000, Sid Boyce wrote:
> CHK kernel/config_data.h
> CC [M] drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.o
> drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c: In function
> ‘nvd0_dmaobj_bind’:
> drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c:54:8: error:
> ‘GM204_DISP_CORE_CHANNEL_DMA’ undeclared (first use in this function)
> case GM204_DISP_CORE_CHANNEL_DMA:
>...
2014 Dec 22
0
3.19.0-rc1 nouvea build failure on GeForce GT 610 only
On 22/12/14 13:54, Paul Bolle wrote:
> On Mon, 2014-12-22 at 14:37 +0100, Paul Bolle wrote:
>> On Mon, 2014-12-22 at 13:01 +0000, Sid Boyce wrote:
>>> CHK kernel/config_data.h
>>> CC [M] drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.o
>>> drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c: In function
>>> ‘nvd0_dmaobj_bind’:
>>> drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c:54:8: error:
>>> ‘GM204_DISP_CORE_CHANNEL_DMA’ undeclared (first use in this function)
>>>...
2014 Apr 02
1
CH7007A (AKA CH7006) TV OUT Support for NV11 (NVidia GeForce2 Go Dell I8K Laptop)
...uveau D[ PCIGART][0000:01:00.0] reset
[ 4.258381] nouveau D[ PCIGART][0000:01:00.0] initialised
[ 4.260447] nouveau D[ CLK][0000:01:00.0] created
[ 4.260461] nouveau [ CLK][0000:01:00.0] --:
[ 4.260645] nouveau D[ CLK][0000:01:00.0] initialised
[ 4.264184] nouveau D[ DMAOBJ][0000:01:00.0] created
[ 4.264197] nouveau D[ DMAOBJ][0000:01:00.0] reset
[ 4.264215] nouveau D[ PFIFO][0000:01:00.0] created
[ 4.264224] nouveau D[ PFIFO][0000:01:00.0] reset
[ 4.264233] nouveau D[ SW][0000:01:00.0] created
[ 4.264239] nouveau D[ SW][0000:01:00.0] res...
2014 Apr 01
3
CH7007A (AKA CH7006) TV OUT Support for NV11 (NVidia GeForce2 Go Dell I8K Laptop)
> On Tue, Apr 01, 2014 at 02:53:02PM -0400, Ilia Mirkin wrote:
>I believe that ch7006 is the only external encoder that's supposed to
>work, so you're in luck. It sounds like it passes the nv04_tv_identify
>stage of nv04_tv_create -- perhaps it fails later? Although based on
>the prints, it's even doing dpms stuff (but it hits _detect a second
>time... odd). Try
2017 May 02
0
drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c:124:: possible unintended fallthrough ?
Hello there,
drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c:124:18: warning: this statement may fall through [-Wimplicit-fallthrough=]
Source code is
switch (dmaobj->base.access) {
case NV_MEM_ACCESS_RO:
dmaobj->flags0 |= 0x00004000;
break;
case NV_MEM_ACCESS_WO:
dmaobj->flags0 |= 0x00008000;
case NV_MEM_ACCESS_RW:
dmaobj->flags2 |= 0x00000002;
break;
default:
return -EINVAL;
}
Su...
2014 Feb 15
3
[RFC PATCH] drm/nouveau: split off nvc0 compilation
...nv50.o
-nouveau-y += core/subdev/vm/nvc0.o
+nouveau-$(CONFIG_DRM_NOUVEAU_NVC0) += core/subdev/vm/nvc0.o
nouveau-y += core/subdev/volt/base.o
nouveau-y += core/subdev/volt/gpio.o
nouveau-y += core/subdev/volt/nv40.o
@@ -185,15 +185,15 @@ nouveau-y += core/engine/xtensa.o
nouveau-y += core/engine/dmaobj/base.o
nouveau-y += core/engine/dmaobj/nv04.o
nouveau-y += core/engine/dmaobj/nv50.o
-nouveau-y += core/engine/dmaobj/nvc0.o
-nouveau-y += core/engine/dmaobj/nvd0.o
+nouveau-$(CONFIG_DRM_NOUVEAU_NVC0) += core/engine/dmaobj/nvc0.o
+nouveau-$(CONFIG_DRM_NOUVEAU_NVC0) += core/engine/dmaobj/nvd0.o
n...
2014 Feb 15
0
[RFC PATCH] drm/nouveau: split off nvc0 compilation
...ev/vm/nvc0.o
> +nouveau-$(CONFIG_DRM_NOUVEAU_NVC0) += core/subdev/vm/nvc0.o
> nouveau-y += core/subdev/volt/base.o
> nouveau-y += core/subdev/volt/gpio.o
> nouveau-y += core/subdev/volt/nv40.o
> @@ -185,15 +185,15 @@ nouveau-y += core/engine/xtensa.o
> nouveau-y += core/engine/dmaobj/base.o
> nouveau-y += core/engine/dmaobj/nv04.o
> nouveau-y += core/engine/dmaobj/nv50.o
> -nouveau-y += core/engine/dmaobj/nvc0.o
> -nouveau-y += core/engine/dmaobj/nvd0.o
> +nouveau-$(CONFIG_DRM_NOUVEAU_NVC0) += core/engine/dmaobj/nvc0.o
> +nouveau-$(CONFIG_DRM_NOUVEAU_NVC0) +...
2018 Oct 17
2
[PATCH] drm/nouveau/nvkm: mark expected switch fall-throughs
...break;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c
index 49ef7e5..7f1adab 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c
@@ -122,6 +122,7 @@ nv04_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass,
break;
case NV_MEM_ACCESS_WO:
dmaobj->flags0 |= 0x00008000;
+ /* fall through */
case NV_MEM_ACCESS_RW:
dmaobj->flags2 |= 0x00000002;
break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c b/drivers/gpu/...
2023 Dec 03
1
Meaning of the engines in paramaters of nouveau module
In https://nouveau.freedesktop.org/KernelModuleParameters.html, there is:
Here is a list of engines:
DEVICE
DMAOBJ
PBSP
PCE0
PCE1
PCE2
PCRYPT
PDISP
PFIFO
PGRAPH
PMPEG
PPM
PPPP
PVP
SW
Also, in debug:
CLIENT
I have tried to find a description of those.
https://envytools.readthedocs.io/en/latest/
help a bit, but I don't find a precise correlation.
https:...
2023 Dec 05
1
Meaning of the engines in paramaters of nouveau module
On Mon, 4 Dec 2023 at 05:04, Paul Dufresne <dufresnep at zoho.com> wrote:
>
> In https://nouveau.freedesktop.org/KernelModuleParameters.html, there is:
> Here is a list of engines:
> DEVICE
> DMAOBJ
> PBSP
> PCE0
> PCE1
> PCE2
> PCRYPT
> PDISP
> PFIFO
> PGRAPH
> PMPEG
> PPM
> PPPP
> PVP
> SW
> Also, in debug:
> CLIENT
>
> I have tried to find a description of those.
> https://envytools....
2014 Mar 23
0
[PATCH] drm/nouveau: allow nv04/nv50/nvc0+ parts of the driver to be separated
...re/subdev/volt/nv40.o
-nouveau-y += core/engine/falcon.o
-nouveau-y += core/engine/xtensa.o
+nouveau-$(CONFIG_DRM_NOUVEAU_NV50) += core/engine/falcon.o
+nouveau-$(CONFIG_DRM_NOUVEAU_NVC0) += core/engine/falcon.o
+nouveau-$(CONFIG_DRM_NOUVEAU_NV50) += core/engine/xtensa.o
nouveau-y += core/engine/dmaobj/base.o
-nouveau-y += core/engine/dmaobj/nv04.o
-nouveau-y += core/engine/dmaobj/nv50.o
-nouveau-y += core/engine/dmaobj/nvc0.o
-nouveau-y += core/engine/dmaobj/nvd0.o
-nouveau-y += core/engine/bsp/nv84.o
-nouveau-y += core/engine/bsp/nv98.o
-nouveau-y += core/engine/bsp/nvc0.o
-nouveau-y += core/en...
2018 Jun 27
0
[PATCH] drm/nouveau/nvkm: mark expected switch fall-throughs
...break;
}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c
index 49ef7e5..7f1adab 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c
@@ -122,6 +122,7 @@ nv04_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass,
break;
case NV_MEM_ACCESS_WO:
dmaobj->flags0 |= 0x00008000;
+ /* fall through */
case NV_MEM_ACCESS_RW:
dmaobj->flags2 |= 0x00000002;
break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c b/drivers/gpu/...
2019 Jan 10
0
[PATCH] drm/nouveau/nvkm: mark expected switch fall-throughs
...-git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c
> index 49ef7e5..7f1adab 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c
> +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c
> @@ -122,6 +122,7 @@ nv04_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass,
> break;
> case NV_MEM_ACCESS_WO:
> dmaobj->flags0 |= 0x00008000;
> + /* fall through */
> case NV_MEM_ACCESS_RW:
> dmaobj->flags2 |= 0x00000002;
> break;
> diff --git a/drivers/gpu/drm/...
2020 Jul 07
3
[PATCH][next] drm/nouveau: Use fallthrough pseudo-keyword
...}
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c
index 7f1adab21a5f..5159d5df20a2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c
@@ -122,7 +122,7 @@ nv04_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass,
break;
case NV_MEM_ACCESS_WO:
dmaobj->flags0 |= 0x00008000;
- /* fall through */
+ fallthrough;
case NV_MEM_ACCESS_RW:
dmaobj->flags2 |= 0x00000002;
break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04....
2020 Jul 08
0
[PATCH][next] drm/nouveau: Use fallthrough pseudo-keyword
...vers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c
> index 7f1adab21a5f..5159d5df20a2 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c
> +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c
> @@ -122,7 +122,7 @@ nv04_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass,
> break;
> case NV_MEM_ACCESS_WO:
> dmaobj->flags0 |= 0x00008000;
> - /* fall through */
> + fallthrough;
> case NV_MEM_ACCESS_RW:
>...
2013 Jun 23
0
[PATCH v2] nouveau: Load firmware for BSP/VP engines on NV84-NV96, NVA0
...-23,6 +23,7 @@ nouveau-y += core/core/parent.o
nouveau-y += core/core/printk.o
nouveau-y += core/core/ramht.o
nouveau-y += core/core/subdev.o
+nouveau-y += core/core/xtensa.o
nouveau-y += core/subdev/bar/base.o
nouveau-y += core/subdev/bar/nv50.o
@@ -135,6 +136,7 @@ nouveau-y += core/engine/dmaobj/nv50.o
nouveau-y += core/engine/dmaobj/nvc0.o
nouveau-y += core/engine/dmaobj/nvd0.o
nouveau-y += core/engine/bsp/nv84.o
+nouveau-y += core/engine/bsp/nv98.o
nouveau-y += core/engine/bsp/nvc0.o
nouveau-y += core/engine/bsp/nve0.o
nouveau-y += core/engine/copy/nva3.o
@@ -209,6 +211,7 @@ nouvea...
2013 Nov 09
2
[PATCH] drm/nouveau/clk: Initial implementation for reclocking NVAA/NVAC
Reclocking of NVAA/NVAC is substantially different from NV50+, enough to justify a separate clock implementation. This code is a forward-port of reclocking code that has been sitting in a branch for a while, and has been tested on my NVAC. Traces show no significant reasons why this shouldn't work on NVAA, but testers are always welcome. And since these are IGPs without dedicated RAM to