search for: dma_pfn_offset

...k you mean bars. That's unrelated to DMA. Of course it matters. If the device always needs an offset in the DMA addresses it is completely related to DMA. For some examples take a look at: arch/x86/pci/sta2x11-fixup.c arch/mips/include/asm/mach-ath25/dma-coherence.h or anything setting dma_pfn_offset. > > Worse so some of these offsets might be based on > > banks, e.g. on the broadcom bmips platform. It also deals > > with bitmask in physical addresses related to memory encryption > > like AMD SEV. I'd be really curious how for example the > > Intel vir...

On Wed, Jun 06, 2018 at 10:23:06PM -0700, Christoph Hellwig wrote: > On Thu, May 31, 2018 at 08:43:58PM +0300, Michael S. Tsirkin wrote: > > Pls work on a long term solution. Short term needs can be served by > > enabling the iommu platform in qemu. > > So, I spent some time looking at converting virtio to dma ops overrides, > and the current virtio spec, and the sad

On Wed, Jun 06, 2018 at 10:23:06PM -0700, Christoph Hellwig wrote: > On Thu, May 31, 2018 at 08:43:58PM +0300, Michael S. Tsirkin wrote: > > Pls work on a long term solution. Short term needs can be served by > > enabling the iommu platform in qemu. > > So, I spent some time looking at converting virtio to dma ops overrides, > and the current virtio spec, and the sad

Hi all, this series replaced the DMA_ATTR_NON_CONSISTENT flag to dma_alloc_attrs with a separate new dma_alloc_pages API, which is available on all platforms. In addition to cleaning up the convoluted code path, this ensures that other drivers that have asked for better support for non-coherent DMA to pages with incurring bounce buffering over can finally be properly supported. I'm still a