Displaying 7 results from an estimated 7 matches for "dma_idx".
2015 Apr 13
3
[PATCH v4] pmu/gk20a: PMU boot support
...t nvkm_vm *vm;
+};
+
+/*Choices for pmu_state*/
+enum {
+ PMU_STATE_OFF, /*0 PMU is off */
+ PMU_STATE_STARTING, /*1 PMU is on, but not booted */
+ PMU_STATE_INIT_RECEIVED /*2 PMU init message received */
+};
+
+struct pmu_mem_gk20a {
+ u32 dma_base;
+ u8 dma_offset;
+ u8 dma_idx;
+ u16 fb_size;
+};
+
+struct pmu_cmdline_args_gk20a {
+ u32 cpu_freq_hz; /* Frequency of the clock driving PMU */
+ u32 falc_trace_size; /* falctrace buffer size (bytes) */
+ u32 falc_trace_dma_base; /* 256-byte block address */
+ u32 falc_trace_dma_idx; /* dmaIdx for DMA operations */
+ u8 sec...
2015 Apr 08
3
[PATCH V2] pmu/gk20a: PMU boot support.
...nvkm_vm *vm;
+};
+
+/* Choices for pmu_state */
+enum {
+ PMU_STATE_OFF, /*0 PMU is off */
+ PMU_STATE_STARTING, /*1 PMU is on, but not booted */
+ PMU_STATE_INIT_RECEIVED /*2 PMU init message received */
+};
+
+struct pmu_mem_gk20a {
+ u32 dma_base;
+ u8 dma_offset;
+ u8 dma_idx;
+ u16 fb_size;
+};
+
+struct pmu_cmdline_args_gk20a {
+ u32 cpu_freq_hz; /* Frequency of the clock driving PMU */
+ u32 falc_trace_size; /* falctrace buffer size (bytes) */
+ u32 falc_trace_dma_base; /* 256-byte block address */
+ u32 falc_trace_dma_idx; /* dmaIdx for DMA operations */
+ u8 sec...
2015 Apr 30
2
[PATCH v4] pmu/gk20a: PMU boot support
.../
>> + PMU_STATE_STARTING, /*1 PMU is on, but not booted */
>> + PMU_STATE_INIT_RECEIVED /*2 PMU init message received */
>> +};
>> +
>> +struct pmu_mem_gk20a {
>> + u32 dma_base;
>> + u8 dma_offset;
>> + u8 dma_idx;
>> + u16 fb_size;
>> +};
>> +
>> +struct pmu_cmdline_args_gk20a {
>> + u32 cpu_freq_hz; /* Frequency of the clock driving
>> PMU */
>> + u32 falc_trace_size; /* falctrace buffer size (bytes)
>> */
>>...
2016 Nov 21
33
[PATCH v4 0/33] Secure Boot refactoring / signed PMU firmware support for GM20B
This revision includes initial signed PMU firmware support for GM20B
(Tegra X1). This PMU code will also be used as a basis for dGPU signed
PMU firmware support.
With the PMU code, the refactoring of secure boot should also make
more sense.
ACR (secure boot) support is now separated by the driver version it
originates from. This separation allows to run any version of the ACR
on any chip,
2015 Mar 11
0
[PATCH] pmu/gk20a: PMU boot support.
...+
> + /* TBD: load all other surfaces */
> + cmdline_args.falc_trace_size = GK20A_PMU_TRACE_BUFSIZE;
> + cmdline_args.falc_trace_dma_base =
> + u64_lo32(pmu->trace_buf.pmubufvma.offset >> 8);
> + cmdline_args.falc_trace_dma_idx = GK20A_PMU_DMAIDX_VIRT;
> + cmdline_args.cpu_freq_hz = 204;
> + cmdline_args.secure_mode = 0;
> +
> + addr_args = (nv_rd32(ppmu, 0x0010a108) >> 9) & 0x1ff;
> + addr_args = addr_args << GK20A_PMU_DMEM_BLKSIZE2;
> + addr_args -= sizeof(...
2015 Mar 11
3
[PATCH] pmu/gk20a: PMU boot support.
...ppmuvm->mem->addr >> 12 |
+ 0x1 << 30 |
+ 0x20000000);
+
+ /* TBD: load all other surfaces */
+ cmdline_args.falc_trace_size = GK20A_PMU_TRACE_BUFSIZE;
+ cmdline_args.falc_trace_dma_base =
+ u64_lo32(pmu->trace_buf.pmubufvma.offset >> 8);
+ cmdline_args.falc_trace_dma_idx = GK20A_PMU_DMAIDX_VIRT;
+ cmdline_args.cpu_freq_hz = 204;
+ cmdline_args.secure_mode = 0;
+
+ addr_args = (nv_rd32(ppmu, 0x0010a108) >> 9) & 0x1ff;
+ addr_args = addr_args << GK20A_PMU_DMEM_BLKSIZE2;
+ addr_args -= sizeof(struct pmu_cmdline_args_gk20a);
+ nv_debug(ppmu, "initi...
2015 Mar 12
2
[PATCH] pmu/gk20a: PMU boot support.
...+
> + /* TBD: load all other surfaces */
> + cmdline_args.falc_trace_size = GK20A_PMU_TRACE_BUFSIZE;
> + cmdline_args.falc_trace_dma_base =
> + u64_lo32(pmu->trace_buf.pmubufvma.offset >> 8);
> + cmdline_args.falc_trace_dma_idx = GK20A_PMU_DMAIDX_VIRT;
> + cmdline_args.cpu_freq_hz = 204;
> + cmdline_args.secure_mode = 0;
> +
> + addr_args = (nv_rd32(ppmu, 0x0010a108) >> 9) & 0x1ff;
> + addr_args = addr_args << GK20A_PMU_DMEM_BLKSIZE2;
> + addr_args -= sizeof(...