search for: dma_attr_write_barri

...> --- a/include/linux/dma-mapping.h > +++ b/include/linux/dma-mapping.h > @@ -5,13 +5,25 @@ > +/** > + * List of possible attributes associated with a DMA mapping. The semantics > + * of each attribute should be defined in Documentation/DMA-attributes.txt. > + */ > +#define DMA_ATTR_WRITE_BARRIER (1UL << 1) Any particular reason they start at 2, not 1? > +#define DMA_ATTR_WEAK_ORDERING (1UL << 2) > +#define DMA_ATTR_WRITE_COMBINE (1UL << 3) > +#define DMA_ATTR_NON_CONSISTENT (1UL << 4) > +#define DMA_ATTR_NO_KERN...

...ch/ia64/sn/pci/pci_dma.c @@ -183,14 +183,11 @@ static dma_addr_t sn_dma_map_page(struct device *dev, struct page *page, unsigned long phys_addr; struct pci_dev *pdev = to_pci_dev(dev); struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev); - int dmabarr; - - dmabarr = dma_get_attr(DMA_ATTR_WRITE_BARRIER, attrs); BUG_ON(!dev_is_pci(dev)); phys_addr = __pa(cpu_addr); - if (dmabarr) + if (attrs & DMA_ATTR_WRITE_BARRIER) dma_addr = provider->dma_map_consistent(pdev, phys_addr, size, SN_DMA_ADDR_PHYS); else @@ -280,9 +277,6 @@ static int sn_dma_map_sg(struct device *dev, s...

...tes.txt index e8cf9cf873b3..2d455a5cf671 100644 --- a/Documentation/DMA-attributes.txt +++ b/Documentation/DMA-attributes.txt @@ -2,7 +2,7 @@ ============== This document describes the semantics of the DMA attributes that are -defined in linux/dma-attrs.h. +defined in linux/dma-mapping.h. DMA_ATTR_WRITE_BARRIER ---------------------- diff --git a/include/linux/dma-attrs.h b/include/linux/dma-attrs.h deleted file mode 100644 index 5246239a4953..000000000000 --- a/include/linux/dma-attrs.h +++ /dev/null @@ -1,71 +0,0 @@ -#ifndef _DMA_ATTR_H -#define _DMA_ATTR_H - -#include <linux/bitmap.h> -#includ...

...n"); return -ENOMEM; diff --git a/lib/include/nvif/os.h b/lib/include/nvif/os.h index f6391a5..b4d307e 100644 --- a/lib/include/nvif/os.h +++ b/lib/include/nvif/os.h @@ -683,6 +683,37 @@ dma_free_coherent(struct device *dev, size_t sz, void *vaddr, dma_addr_t bus) { } +enum dma_attr { + DMA_ATTR_WRITE_BARRIER, + DMA_ATTR_WEAK_ORDERING, + DMA_ATTR_WRITE_COMBINE, + DMA_ATTR_NON_CONSISTENT, + DMA_ATTR_NO_KERNEL_MAPPING, + DMA_ATTR_SKIP_CPU_SYNC, + DMA_ATTR_FORCE_CONTIGUOUS, + DMA_ATTR_MAX, +}; + +struct dma_attrs { +}; + +static inline void init_dma_attrs(struct dma_attrs *attrs) {} +static inline void d...

...return -ENOMEM; diff --git a/lib/include/nvif/os.h b/lib/include/nvif/os.h index f6391a58fd11..b4d307e3ac44 100644 --- a/lib/include/nvif/os.h +++ b/lib/include/nvif/os.h @@ -683,6 +683,37 @@ dma_free_coherent(struct device *dev, size_t sz, void *vaddr, dma_addr_t bus) { } +enum dma_attr { + DMA_ATTR_WRITE_BARRIER, + DMA_ATTR_WEAK_ORDERING, + DMA_ATTR_WRITE_COMBINE, + DMA_ATTR_NON_CONSISTENT, + DMA_ATTR_NO_KERNEL_MAPPING, + DMA_ATTR_SKIP_CPU_SYNC, + DMA_ATTR_FORCE_CONTIGUOUS, + DMA_ATTR_MAX, +}; + +struct dma_attrs { +}; + +static inline void init_dma_attrs(struct dma_attrs *attrs) {} +static inline void d...

...os.h b/lib/include/nvif/os.h > index f6391a58fd11..b4d307e3ac44 100644 > --- a/lib/include/nvif/os.h > +++ b/lib/include/nvif/os.h > @@ -683,6 +683,37 @@ dma_free_coherent(struct device *dev, size_t sz, void *vaddr, dma_addr_t bus) > { > } > > +enum dma_attr { > + DMA_ATTR_WRITE_BARRIER, > + DMA_ATTR_WEAK_ORDERING, > + DMA_ATTR_WRITE_COMBINE, > + DMA_ATTR_NON_CONSISTENT, > + DMA_ATTR_NO_KERNEL_MAPPING, > + DMA_ATTR_SKIP_CPU_SYNC, > + DMA_ATTR_FORCE_CONTIGUOUS, > + DMA_ATTR_MAX, > +}; > + > +struct dma_attrs...

Hi, This is third approach (complete this time) for replacing struct dma_attrs with unsigned long. The main patch (2/45) doing the change is split into many subpatches for easier review (3-43). They should be squashed together when applying. *Important:* Patchset is *only* build tested on allyesconfigs: ARM, ARM64, i386, x86_64 and powerpc. Please provide reviewes and tests for other

Thanks Ilia for the v2 review! Here is the v3 of this IOMMU support for GK20A series. Changes since v2: - Cleaner changes for ltc - Fixed typos in gk20a instmem IOMMU comments Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into nouveau_display.c and nv84_fence.c. Original cover letter: Patches 1-3 make the presence of a RAM device optional, and remove

Changes since v3: - Use a single dma_attr for all DMA-API allocations in instmem instead of one per allocation - Use device.info.ram_size instead of pfb->ram to check whether VRAM is present outside of nvkm Changes since v2: - Cleaner changes for ltc - Fixed typos in gk20a instmem IOMMU comments Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into

Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into nouveau_display.c and nv84_fence.c. Original cover letter: Patches 1-3 make the presence of a RAM device optional, and remove GK20A's dummy RAM driver we were using so far. On chips using shared memory, such a device can confuse the driver into moving objects where there is no need to, and can trick

A series I have waited too long to submit, and the recent refactoring made me pay the price of my perfectionism, so here are the features that are at least completed Patches 1-3 make the presence of a RAM device optional, and remove GK20A's dummy RAM driver we were using so far. On chips using shared memory, such a device can confuse the driver into moving objects where there is no need to,