search for: dma_attr_weak_ord

Hard-coded value of DMA_ATTR_WEAK_ORDERING is then compared with the symbol. This will stop matching if the value of symbol is changed (when switching DMA attributes to unsigned long). Signed-off-by: Krzysztof Kozlowski <k.kozlowski at samsung.com> --- arch/powerpc/platforms/cell/iommu.c | 2 +- 1 file changed, 1 insertion(+),...

...++ b/arch/powerpc/platforms/cell/iommu.c @@ -193,7 +193,7 @@ static int tce_build_cell(struct iommu_table *tbl, long index, long npages, base_pte = CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | CBE_IOPTE_M | CBE_IOPTE_SO_RW | (window->ioid & CBE_IOPTE_IOID_Mask); #endif - if (unlikely(dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs))) + if (unlikely(attrs & DMA_ATTR_WEAK_ORDERING)) base_pte &= ~CBE_IOPTE_SO_RW; io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset); @@ -600,7 +600,7 @@ static dma_addr_t dma_fixed_map_page(struct device *dev, struct page *page, enum dma_dat...

...t; + init_dma_attrs(&node->attrs); > + /* > + * We will access this memory through PRAMIN and thus do not need a > + * consistent CPU pointer > + */ > + dma_set_attr(DMA_ATTR_NON_CONSISTENT, &node->attrs); > + dma_set_attr(DMA_ATTR_WEAK_ORDERING, &node->attrs); > + dma_set_attr(DMA_ATTR_WRITE_COMBINE, &node->attrs); > + dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &node->attrs); I wonder, is it possible to have a per-priv version of this instead of per-object? The kernel's function prototypes ar...

...); return -ENOMEM; @@ -597,10 +597,9 @@ gk20a_instmem_new(struct nvkm_device *device, int index, nvkm_info(&imem->base.subdev, "using IOMMU\n"); } else { - init_dma_attrs(&imem->attrs); - dma_set_attr(DMA_ATTR_NON_CONSISTENT, &imem->attrs); - dma_set_attr(DMA_ATTR_WEAK_ORDERING, &imem->attrs); - dma_set_attr(DMA_ATTR_WRITE_COMBINE, &imem->attrs); + imem->attrs = DMA_ATTR_NON_CONSISTENT | + DMA_ATTR_WEAK_ORDERING | + DMA_ATTR_WRITE_COMBINE; nvkm_info(&imem->base.subdev, "using DMA API\n"); } -- 1.9.1

...); return -ENOMEM; @@ -597,10 +597,9 @@ gk20a_instmem_new(struct nvkm_device *device, int index, nvkm_info(&imem->base.subdev, "using IOMMU\n"); } else { - init_dma_attrs(&imem->attrs); - dma_set_attr(DMA_ATTR_NON_CONSISTENT, &imem->attrs); - dma_set_attr(DMA_ATTR_WEAK_ORDERING, &imem->attrs); - dma_set_attr(DMA_ATTR_WRITE_COMBINE, &imem->attrs); + imem->attrs = DMA_ATTR_NON_CONSISTENT | + DMA_ATTR_WEAK_ORDERING | + DMA_ATTR_WRITE_COMBINE; nvkm_info(&imem->base.subdev, "using DMA API\n"); } -- 1.9.1

...); return -ENOMEM; @@ -597,10 +597,9 @@ gk20a_instmem_new(struct nvkm_device *device, int index, nvkm_info(&imem->base.subdev, "using IOMMU\n"); } else { - init_dma_attrs(&imem->attrs); - dma_set_attr(DMA_ATTR_NON_CONSISTENT, &imem->attrs); - dma_set_attr(DMA_ATTR_WEAK_ORDERING, &imem->attrs); - dma_set_attr(DMA_ATTR_WRITE_COMBINE, &imem->attrs); + imem->attrs = DMA_ATTR_NON_CONSISTENT | + DMA_ATTR_WEAK_ORDERING | + DMA_ATTR_WRITE_COMBINE; nvkm_info(&imem->base.subdev, "using DMA API\n"); } -- 1.9.1

...v, npages << PAGE_SHIFT, - &node->handle, GFP_KERNEL); + init_dma_attrs(&node->attrs); + /* + * We will access this memory through PRAMIN and thus do not need a + * consistent CPU pointer + */ + dma_set_attr(DMA_ATTR_NON_CONSISTENT, &node->attrs); + dma_set_attr(DMA_ATTR_WEAK_ORDERING, &node->attrs); + dma_set_attr(DMA_ATTR_WRITE_COMBINE, &node->attrs); + dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &node->attrs); + + node->cpuaddr = dma_alloc_attrs(dev, npages << PAGE_SHIFT, + &node->handle, GFP_KERNEL, + &node->attrs); if...

...v, npages << PAGE_SHIFT, - &node->handle, GFP_KERNEL); + init_dma_attrs(&node->attrs); + /* + * We will access this memory through PRAMIN and thus do not need a + * consistent CPU pointer + */ + dma_set_attr(DMA_ATTR_NON_CONSISTENT, &node->attrs); + dma_set_attr(DMA_ATTR_WEAK_ORDERING, &node->attrs); + dma_set_attr(DMA_ATTR_WRITE_COMBINE, &node->attrs); + dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &node->attrs); + + node->cpuaddr = dma_alloc_attrs(dev, npages << PAGE_SHIFT, + &node->handle, GFP_KERNEL, + &node->attrs); if...

...Rebased on next-20160607. For easier testing the patchset is available here: repo: https://github.com/krzk/linux branch: for-next/dma-attrs-const-v4 Changes since v3 ================ 1. Collect some acks. 2. Drop wrong patch 1/45 ("powerpc: dma-mapping: Don't hard-code the value of DMA_ATTR_WEAK_ORDERING"). 3. Minor fix pointed out by Michael Ellerman. Changes since v2 ================ 1. Follow Christoph Hellwig's comments (don't use BIT add documentation, remove dma_get_attr). Rationale ========= The dma-mapping core and the implementations do not change the DMA attribute...

...* > + * List of possible attributes associated with a DMA mapping. The semantics > + * of each attribute should be defined in Documentation/DMA-attributes.txt. > + */ > +#define DMA_ATTR_WRITE_BARRIER (1UL << 1) Any particular reason they start at 2, not 1? > +#define DMA_ATTR_WEAK_ORDERING (1UL << 2) > +#define DMA_ATTR_WRITE_COMBINE (1UL << 3) > +#define DMA_ATTR_NON_CONSISTENT (1UL << 4) > +#define DMA_ATTR_NO_KERNEL_MAPPING (1UL << 5) > +#define DMA_ATTR_SKIP_CPU_SYNC (1UL << 6) > +#define...

...on the stack and passing pointer to it to dma_set_attr(), just set the bits. 2. It brings safeness and checking for const correctness because the attributes are passed by value. Best regards, Krzysztof Krzysztof Kozlowski (45): powerpc: dma-mapping: Don't hard-code the value of DMA_ATTR_WEAK_ORDERING dma-mapping: Use unsigned long for dma_attrs alpha: dma-mapping: Use unsigned long for dma_attrs arc: dma-mapping: Use unsigned long for dma_attrs ARM: dma-mapping: Use unsigned long for dma_attrs arm64: dma-mapping: Use unsigned long for dma_attrs avr32: dma-mapping: Use unsigned...

...ap.h> -#include <linux/bitops.h> -#include <linux/bug.h> - -/** - * an enum dma_attr represents an attribute associated with a DMA - * mapping. The semantics of each attribute should be defined in - * Documentation/DMA-attributes.txt. - */ -enum dma_attr { - DMA_ATTR_WRITE_BARRIER, - DMA_ATTR_WEAK_ORDERING, - DMA_ATTR_WRITE_COMBINE, - DMA_ATTR_NON_CONSISTENT, - DMA_ATTR_NO_KERNEL_MAPPING, - DMA_ATTR_SKIP_CPU_SYNC, - DMA_ATTR_FORCE_CONTIGUOUS, - DMA_ATTR_ALLOC_SINGLE_PAGES, - DMA_ATTR_MAX, -}; - -#define __DMA_ATTRS_LONGS BITS_TO_LONGS(DMA_ATTR_MAX) - -/** - * struct dma_attrs - an opaque contain...

Changes since v3: - Use a single dma_attr for all DMA-API allocations in instmem instead of one per allocation - Use device.info.ram_size instead of pfb->ram to check whether VRAM is present outside of nvkm Changes since v2: - Cleaner changes for ltc - Fixed typos in gk20a instmem IOMMU comments Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into

...iommu_bit = tdev->func->iommu_bit; nvkm_info(&imem->base.subdev, "using IOMMU\n"); } else { init_dma_attrs(&imem->attrs); - /* We will access the memory through our own mapping */ dma_set_attr(DMA_ATTR_NON_CONSISTENT, &imem->attrs); dma_set_attr(DMA_ATTR_WEAK_ORDERING, &imem->attrs); dma_set_attr(DMA_ATTR_WRITE_COMBINE, &imem->attrs); - dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &imem->attrs); - imem->cpu_map = gk20a_instobj_cpu_map_dma; nvkm_info(&imem->base.subdev, "using DMA API\n"); } diff --git a/lib/i...

...d by Robin Murphy. 3. Applied changes from Bart Van Assche's comment. 4. More tests and builds (using https://www.kernel.org/pub/tools/crosstool/). Changes since v3 ================ 1. Collect some acks. 2. Drop wrong patch 1/45 ("powerpc: dma-mapping: Don't hard-code the value of DMA_ATTR_WEAK_ORDERING"). 3. Minor fix pointed out by Michael Ellerman. Changes since v2 ================ 1. Follow Christoph Hellwig's comments (don't use BIT add documentation, remove dma_get_attr). Rationale ========= The dma-mapping core and the implementations do not change the DMA attribute...

Thanks Ilia for the v2 review! Here is the v3 of this IOMMU support for GK20A series. Changes since v2: - Cleaner changes for ltc - Fixed typos in gk20a instmem IOMMU comments Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into nouveau_display.c and nv84_fence.c. Original cover letter: Patches 1-3 make the presence of a RAM device optional, and remove

..._bit; > > nvkm_info(&imem->base.subdev, "using IOMMU\n"); > } else { > init_dma_attrs(&imem->attrs); > - /* We will access the memory through our own mapping */ > dma_set_attr(DMA_ATTR_NON_CONSISTENT, &imem->attrs); > dma_set_attr(DMA_ATTR_WEAK_ORDERING, &imem->attrs); > dma_set_attr(DMA_ATTR_WRITE_COMBINE, &imem->attrs); > - dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &imem->attrs); > - imem->cpu_map = gk20a_instobj_cpu_map_dma; > > nvkm_info(&imem->base.subdev, "using DMA API\n"...

...om Bart Van Assche's comment. > 4. More tests and builds (using https://www.kernel.org/pub/tools/crosstool/). > > > Changes since v3 > ================ > 1. Collect some acks. > 2. Drop wrong patch 1/45 ("powerpc: dma-mapping: Don't hard-code > the value of DMA_ATTR_WEAK_ORDERING"). > 3. Minor fix pointed out by Michael Ellerman. > > > Changes since v2 > ================ > 1. Follow Christoph Hellwig's comments (don't use BIT add > documentation, remove dma_get_attr). > > > Rationale > ========= > The dma-mapping...

...d by Robin Murphy. 3. Applied changes from Bart Van Assche's comment. 4. More tests and builds (using https://www.kernel.org/pub/tools/crosstool/). Changes since v3 ================ 1. Collect some acks. 2. Drop wrong patch 1/45 ("powerpc: dma-mapping: Don't hard-code the value of DMA_ATTR_WEAK_ORDERING"). 3. Minor fix pointed out by Michael Ellerman. Changes since v2 ================ 1. Follow Christoph Hellwig's comments (don't use BIT add documentation, remove dma_get_attr). Rationale ========= The dma-mapping core and the implementations do not change the DMA attribute...

Changes since v1: - Add missing else condition in ltc - Remove extra flags that slipped into nouveau_display.c and nv84_fence.c. Original cover letter: Patches 1-3 make the presence of a RAM device optional, and remove GK20A's dummy RAM driver we were using so far. On chips using shared memory, such a device can confuse the driver into moving objects where there is no need to, and can trick