Displaying 2 results from an estimated 2 matches for "divuw".
2018 Dec 14
2
Dealing with information loss for widened integer operations at ISel time
...instructions, so there's no point to using W forms
> if you don't need the sign extension. Unless MULW has lower latency than
> MUL on some CPU?
It only matters when it allows you to avoid an unnecessary sext/zext
of the input operands. Consider the following input:
define i32 @aext_divuw_aext_aext(i32 %a, i32 %b) nounwind {
%1 = udiv i32 %a, %b
ret i32 %1
}
This pattern won't match:
def : Pat<(sext_inreg (udiv (zexti32 GPR:$rs1), (zexti32 GPR:$rs2)), i32),
(DIVUW GPR:$rs1, GPR:$rs2)>;
This pattern would match but is incorrect in the general case (e.g. if
r...
2018 Dec 13
2
Dealing with information loss for widened integer operations at ISel time
As previously discussed in an RFC
<http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, the
RISC-V backend has i64 as the only legal integer type for the RV64 target.
Thanks to variable-sized register class support, this means there is no need
for duplication of either patterns or instruction definitions for RV32 and
RV64. It's worth noting that RV64I is a different base