search for: disp8

...M31 and 16 YMM registers YMM16-YMM31. In order to encode the new registers of 16-31 and the additional instructions, a new encoding prefix called EVEX, which extends the existing VEX encoding, was introduced as shown below: The EVEX encoding format: EVEX Opcode ModR/M [SIB] [Disp32] / [Disp8*N] [Immediate] # of bytes: 4 1 1 1 4 / 1 1 The existing VEX encoding format: [VEX] OPCODE ModR/M [SIB] [DISP] [IMM] # of bytes: 0,2,3 1 1 0,1 0,1,2,4 0,1 Note that the EVEX prefix requires 4 bytes whereas the VEX prefix can take only...

...n order to encode the new registers of 16-31 and the additional > instructions, a new encoding prefix called EVEX, which extends the > existing VEX encoding, was introduced as shown below: > > > > The EVEX encoding format: > > EVEX Opcode ModR/M [SIB] [Disp32] / [Disp8*N] [Immediate] > > # of bytes: 4 1 1 1 4 / 1 1 > > > > The existing VEX encoding format: > > [VEX] OPCODE ModR/M [SIB] [DISP] [IMM] > > # of bytes: 0,2,3 1 1 0,1 0,1,2,4 0,1 > > > > Note that th...

...hus, the order in .bss must be differ against one assembled by GNU as. It might have bugs and I am investigating now. * Trail alignment shim of each section GNU as emits alignment to trail of .text. MC-COFF does not. * MC-COFF does relaxation more strongly I saw a few cases, MC-COFF emits disp8 for branch (although GNU as emits disp32). At a glance, It might be correct. I have not met regression yet. * (Investigating) I saw a few cases; MC-COFF emits quite different instruction sequences. It might be my mistake, still in investigating. I will file one for serious issues. have...

...M31 and 16 YMM registers YMM16-YMM31. In order to encode the new registers of 16-31 and the additional instructions, a new encoding prefix called EVEX, which extends the existing VEX encoding, was introduced as shown below: The EVEX encoding format: EVEX Opcode ModR/M [SIB] [Disp32] / [Disp8*N] [Immediate] # of bytes: 4 1 1 1 4 / 1 1 The existing VEX encoding format: [VEX] OPCODE ModR/M [SIB] [DISP] [IMM] # of bytes: 0,2,3 1 1 0,1 0,1,2,4 0,1 Note that the EVEX prefix requires 4 bytes whereas the VEX prefix can take only...

..."invalid scale for 16-bit memory reference"); + + if (IndexReg16 & 2) + RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1); + else + RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1); + } + + if (Disp.isImm() && isDisp8(Disp.getImm())) { + // Use [REG]+disp8 form if we can, and for [BP] which cannot be encoded. + if (BaseRegNo == N86::EBP || Disp.getImm() != 0) { + EmitByte(ModRMByte(1, RegOpcodeField, RMfield), CurByte, OS); + EmitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte,...

...M31 and 16 YMM registers YMM16-YMM31. In order to encode the new registers of 16-31 and the additional instructions, a new encoding prefix called EVEX, which extends the existing VEX encoding, was introduced as shown below: The EVEX encoding format: EVEX Opcode ModR/M [SIB] [Disp32] / [Disp8*N] [Immediate] # of bytes: 4 1 1 1 4 / 1 1 The existing VEX encoding format: [VEX] OPCODE ModR/M [SIB] [DISP] [IMM] # of bytes: 0,2,3 1 1 0,1 0,1,2,4 0,1 Note that the EVEX prefix requires 4 bytes whereas the VEX prefix can take only...

...reference"); > + > + if (IndexReg16 & 2) > + RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1); > + else > + RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1); > + } > + > + if (Disp.isImm() && isDisp8(Disp.getImm())) { > + // Use [REG]+disp8 form if we can, and for [BP] which cannot be > encoded. > + if (BaseRegNo == N86::EBP || Disp.getImm() != 0) { > + EmitByte(ModRMByte(1, RegOpcodeField, RMfield), CurByte, OS); > + EmitImmediate(Disp, MI.getLoc(...

...case MNEM_PUSH_IB: + c+=2; + break; + + case MNEM_PUSH_EAX: + case MNEM_PUSH_ECX: + case MNEM_PUSH_EDX: + case MNEM_PUSH_EBX: + case MNEM_PUSH_EBP: + case MNEM_PUSH_ESI: + case MNEM_PUSH_EDI: + c+=1; + break; + + case MNEM_LEA: + BUG_ON(*(c+1) != 0x64); /* [--][--]+disp8, %esp */ + BUG_ON(*(c+2) != 0x24); /* none + %esp */ + c+=4; + break; + + default: + /* + * Don't printk - it may acquire spinlocks with + * partially completed VMI translations, causing + * nuclear meltdown of the core. + */ + BUG(); + return; + } + } + +...

...case MNEM_PUSH_IB: + c+=2; + break; + + case MNEM_PUSH_EAX: + case MNEM_PUSH_ECX: + case MNEM_PUSH_EDX: + case MNEM_PUSH_EBX: + case MNEM_PUSH_EBP: + case MNEM_PUSH_ESI: + case MNEM_PUSH_EDI: + c+=1; + break; + + case MNEM_LEA: + BUG_ON(*(c+1) != 0x64); /* [--][--]+disp8, %esp */ + BUG_ON(*(c+2) != 0x24); /* none + %esp */ + c+=4; + break; + + default: + /* + * Don't printk - it may acquire spinlocks with + * partially completed VMI translations, causing + * nuclear meltdown of the core. + */ + BUG(); + return; + } + } + +...

...his instruction use a k-register for masking hasEVEX_Z - Is the k-register used for zero masking or merge masking. hasEVEX_L2 - Should this instruction be encoded with EVEX.L'=1 hasEVEX_B - Should this instruction be encoded with EVEX.b=1 CD8_Form - Format for compressed disp8 for EVEX instructions CD8_EltSize - Element size for compressed displacement hasEVEX_RC - Indicates that EVEX.L'L should be used for embedded rounding control hasNoTrackPrefix - Instruction has notrack prefix. Should only occur on indirect calls and jumps. The X86Inst class should no...

I am attempting to create an instruction which takes a single 64-bit immediate. This doesn't seem like a thing that would exist already (because who needs an instruction which just takes an immediate?) How might I implement this easily? Perhaps I could use a format which encodes a register, which is then unused? Thanks for the help. Gus -------------- next part -------------- An HTML

...if (rm == 5) { - inst = inst + 4; //disp32, skip 4 bytes + if (op16) + inst = inst + 2; //disp16, skip 2 bytes + else + inst = inst + 4; //disp32, skip 4 bytes } break; case 1: inst++; //disp8, skip 1 byte break; case 2: - inst = inst + 4; //disp32, skip 4 bytes + if (op16) + inst = inst + 2; //disp16, skip 2 bytes + else + inst = inst + 4; //disp32, skip 4 bytes + break; } for (i = 0; i < op_s...

...egNo = X86RegisterInfo::getX86RegNum(BaseReg); > + if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) { > + // Emit simple indirect register encoding... [EAX] f.e. > + ++FinalSize; > + // Be pessimistic and assume it's a disp32, not a disp8 > + } else { > + // Emit the most general non-SIB encoding: [REG+disp32] > + ++FinalSize; > + FinalSize += sizeDisplacementField(DispForReloc); > + } > + } > + > + } else { // We need a SIB byte, so start by outputting the ModR/ > M by...

OK, here's a new patch that adds the infrastructure and the implementation for X86, ARM and PPC of GetInstSize and GetFunctionSize. Both functions are virtual functions defined in TargetInstrInfo.h. For X86, I moved some commodity functions from X86CodeEmitter to X86InstrInfo. What do you think? Nicolas Evan Cheng wrote: > > I think both of these belong to TargetInstrInfo. And