search for: disp32

...rs XMM16-XMM31 and 16 YMM registers YMM16-YMM31. In order to encode the new registers of 16-31 and the additional instructions, a new encoding prefix called EVEX, which extends the existing VEX encoding, was introduced as shown below: The EVEX encoding format: EVEX Opcode ModR/M [SIB] [Disp32] / [Disp8*N] [Immediate] # of bytes: 4 1 1 1 4 / 1 1 The existing VEX encoding format: [VEX] OPCODE ModR/M [SIB] [DISP] [IMM] # of bytes: 0,2,3 1 1 0,1 0,1,2,4 0,1 Note that the EVEX prefix requires 4 bytes whereas the VEX prefix can...

...igned char *inst, int op_size) +static inline unsigned long get_immediate(int op16, const unsigned char *inst, int op_size) { int mod, reg, rm; unsigned long val = 0; @@ -183,14 +193,21 @@ switch(mod) { case 0: if (rm == 5) { - inst = inst + 4; //disp32, skip 4 bytes + if (op16) + inst = inst + 2; //disp16, skip 2 bytes + else + inst = inst + 4; //disp32, skip 4 bytes } break; case 1: inst++; //disp8, skip 1 byte break; case 2: -...

...> > In order to encode the new registers of 16-31 and the additional > instructions, a new encoding prefix called EVEX, which extends the > existing VEX encoding, was introduced as shown below: > > > > The EVEX encoding format: > > EVEX Opcode ModR/M [SIB] [Disp32] / [Disp8*N] [Immediate] > > # of bytes: 4 1 1 1 4 / 1 1 > > > > The existing VEX encoding format: > > [VEX] OPCODE ModR/M [SIB] [DISP] [IMM] > > # of bytes: 0,2,3 1 1 0,1 0,1,2,4 0,1 > > > > No...

...ainst one assembled by GNU as. It might have bugs and I am investigating now. * Trail alignment shim of each section GNU as emits alignment to trail of .text. MC-COFF does not. * MC-COFF does relaxation more strongly I saw a few cases, MC-COFF emits disp8 for branch (although GNU as emits disp32). At a glance, It might be correct. I have not met regression yet. * (Investigating) I saw a few cases; MC-COFF emits quite different instruction sequences. It might be my mistake, still in investigating. I will file one for serious issues. have a nice hacking! ...Takumi

...rs XMM16-XMM31 and 16 YMM registers YMM16-YMM31. In order to encode the new registers of 16-31 and the additional instructions, a new encoding prefix called EVEX, which extends the existing VEX encoding, was introduced as shown below: The EVEX encoding format: EVEX Opcode ModR/M [SIB] [Disp32] / [Disp8*N] [Immediate] # of bytes: 4 1 1 1 4 / 1 1 The existing VEX encoding format: [VEX] OPCODE ModR/M [SIB] [DISP] [IMM] # of bytes: 0,2,3 1 1 0,1 0,1,2,4 0,1 Note that the EVEX prefix requires 4 bytes whereas the VEX prefix can...

...unsigned BaseReg = Base.getReg(); > + > + // Is a SIB byte needed? > + if (IndexReg.getReg() == 0 && > + (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != > N86::ESP)) { > + if (BaseReg == 0) { // Just a displacement? > + // Emit special case [disp32] encoding > + ++FinalSize; > + FinalSize += sizeDisplacementField(DispForReloc); > + } else { > + unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg); > + if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) { > + // Emi...

OK, here's a new patch that adds the infrastructure and the implementation for X86, ARM and PPC of GetInstSize and GetFunctionSize. Both functions are virtual functions defined in TargetInstrInfo.h. For X86, I moved some commodity functions from X86CodeEmitter to X86InstrInfo. What do you think? Nicolas Evan Cheng wrote: > > I think both of these belong to TargetInstrInfo. And

...rs XMM16-XMM31 and 16 YMM registers YMM16-YMM31. In order to encode the new registers of 16-31 and the additional instructions, a new encoding prefix called EVEX, which extends the existing VEX encoding, was introduced as shown below: The EVEX encoding format: EVEX Opcode ModR/M [SIB] [Disp32] / [Disp8*N] [Immediate] # of bytes: 4 1 1 1 4 / 1 1 The existing VEX encoding format: [VEX] OPCODE ModR/M [SIB] [DISP] [IMM] # of bytes: 0,2,3 1 1 0,1 0,1,2,4 0,1 Note that the EVEX prefix requires 4 bytes whereas the VEX prefix can...

...https://llvm.org/docs/CodeGenerator.html#x86-addressing-mode The x86 has a very flexible way of accessing memory. It is capable of forming memory addresses of the following expression directly in integer instructions (which use ModR/M addressing): SegmentReg: Base + [1,2,4,8] * IndexReg + Disp32 In order to represent this, LLVM tracks no less than 5 operands for each memory operand of this form. This means that the “load” form of ‘mov’ has the following MachineOperands in this order: Index: 0 | 1 2 3 4 5 Meaning: DestReg, | BaseReg...