search for: disjunct

...history=y", sep="") docId <- xmlTreeParse(getURL(paste(url, search, sep="")), useInternalNodes=TRUE) I want to fetch abstracts containing queryTerm1 AND queryTerm2 Or queryTerm3 OR queryTerm4. The code runs without error, but from the result I find that conjunction and disjunction is not working. Can anyone suggest a correct syntax for doing AND and OR pubmed query? Thanks John [[alternative HTML version deleted]]

Dear all ReadeRs I was finding a quick method to improve test readability adding or constructing (with your help....) one or more function that allow what follow. Please consider Trt<-c(1,1,1,1,2,2,2,2,3,3,3,3,4,4,4,4,5,5,5,5) Block<-c(1,2,3,4,1,2,3,4,1,2,3,4,1,2,3,4,1,2,3,4) AD2DAT<-c(1.44,2.32,1.68,1.28,0.12,0.08,0.24,0.52,0.12,0.08,0.16,0.28,0.16,0.08,0.12,0.12,0.16,0.08,0.32,0.76)

...> if (x > 2 && x < 5) { > ... > } else { > // known: x <= 2 || x >= 5 > // CVP produces a range for x: [5, 3) (no loss of information here at > all) > if (x == 4) ... // CVP folds this to false > } > > > Okay, so it does try to handle simple disjunctions. > So CVP can handle (simple) disjunctive information. Other ValueTracking > analyses handle simple patterns as well, though probably at this time those > can't use this new stuff unless we go all in with e-SSA. > Not sure how to export the information to clients, though. Su...

...then search all of them. > Which means you have to know they exist, for starters, which means keeping it in some sorted order and checking, or some other mechanism. This should not be difficult to implement or use, and seems no less > efficient than any other way of encoding the concept of disjunction in the > hierarchy. > > It is, in actuality, less efficient. For starters, in the inverted representation, you don't have to explicitly represent the things that are children of alias set zero (char in C++'s case), which is quite common. It's also trivial to generate transi...

Hi, I've got some boolean data in a data.frame in the form: X Y Z A B C [1] T T F T F F [2] F T T F F F . . . What I want to do is create a new column which is the logical disjunction of several of the columns. Just like: new.column <- data$X | data$Y | data$Z However I don't want to hard code the particular columns into the expression like that. I've tried using apply row wise with `|` as the function: columns <- c(X,Y,Z) apply(data[,columns], 1,`|`) This d...

Hello there, Offending source code is ????? if(? ( BattVoltage> 129 ) || ( BattVoltage < 144 ) ) Maybe swap || for && would be better. This problem I found by using cppcheck. It said [rhino.c:190]: (warning) Logical disjunction always evaluates to true: BattVoltage> 129 || BattVoltage < 144. Regards David Binderman

...g.com>: > Salut Lapin(c), > > Comment va depuis notre longue discussion sur Solutions Linux ? Plutot bien merci :) > > Lapin(c) wrote: > > > I was exploring a local LDAP solution, as it's for a very large network > (1000 > > sites / 100000 users) we want a disjunction between local administration > for > > machines and global administration for users. > > What do you mean for disjunction between local administration and users ? > > Do you mean : > 1. Separation between directory insertion (etheir user or machine) and > local PC admi...

...al and other types of > expressions to form complex or relational (match) expressions http://git.netfilter.org/nftables/tree/doc/nft.txt#n680 However it's not clear if logical combinations are actually possible? https://bugzilla.netfilter.org/show_bug.cgi?id=1202#c1 explicitly states that disjunctions are definitely not supported, so logical OR, and XOR are right out, and given that I'd say NAND almost certainly is too. The only combining operator for matches is AND. Also, rummaging through the grammar file seems to confirm that there are only _bitwise_ operators. -- You are receivin...

...s to further limit the set of vocabulary terms, then compute the edit distance of strings. 2) deal with synonyms. This can be done by index unnormalized tokens and maintain a query expansion list of multiple vocabulary entries to consider for a certain query term. A query term is then effectively a disjunction of several postings list. Also, an alternative is to do the expansion during index construction. 3) deal with stop words. In modern search engines this is not a good idea, so I think we can just discard it. 4) dividing the queries. User input might be long sentence and contains ?stop words?. Sea...

...you move foo with a, you can > actually clone foo here, change it to be pass-by-value, and promote the > argument inside of it (if you wanted to). > > So you can use this info to, for example, do interprocedural promotion. > > >> Are we instead looking to set a MRI_Must bit, disjunct of MRI_Mod, and >> test for MRI_Ref&MRI_Must or MRI_Mod&MRI_Must? >> > > Yes. > I didn't mean to pick on the example, sorry if that's how it came through. Since the consensus is to expose the Must info in ModRefInfo, I'm trying to figure out how to add it...

This didn't work as I tried with 197.parser. it works without "-Wl,-disable-opt" switch though. [197.parser]$ llvm-gcc analyze-linkage.c and.c build-disjuncts.c extract-links.c fast-match.c idiom.c main.c massage.c parse.c post-process.c print.c prune.c read-dict.c utilities.c xalloc.c word-file.c strncasecmp.c -Wa,-disable-opt -Wl,-disable-opt -lm -o llvm_parser [197.parser]$ opt -inline -inline-threshold=200 < llvm_parser.bc | llc -march=c &gt...

...lias of the live on entry def, etc If I understand correctly, the necessary info for fp in this example is: isMustAlias (CallSite argument a, Value a) && getModRefBehavior(CallSite)== onlyReadsMemory. So adding a MRI_MustMod is insufficient? Are we instead looking to set a MRI_Must bit, disjunct of MRI_Mod, and test for MRI_Ref&MRI_Must or MRI_Mod&MRI_Must? In getModRefInfo(CS, Loc), the MRI_Must bit would then be set if doesAccessArgPointees and ArgAlias == MustAlias for all Args, which seems correct. I may be missing something here, I don't want to dive into the wrong implem...

On Mon, 11 Jul 2005, Long Fei wrote: > > This didn't work as I tried with 197.parser. it works without > "-Wl,-disable-opt" switch though. > > [197.parser]$ llvm-gcc analyze-linkage.c and.c build-disjuncts.c > extract-links.c fast-match.c idiom.c main.c massage.c parse.c post-process.c > print.c prune.c read-dict.c utilities.c xalloc.c word-file.c strncasecmp.c > -Wa,-disable-opt -Wl,-disable-opt -lm -o llvm_parser Note that this will do NO optimization at all, giving you a very very ug...

...and > playing with a representation we aren't actually sure we can make efficient > for this case? > > > I don't see why need to break backward compatibility. Do you have > something specific in mind? Once we extend the TBAA implementation to treat > repeated offsets as disjunction, then we'll extend Clang to emit metadata > for unions in this form. Old IR will work exactly as it does now. > Except the Old IR is irretrievably broken. and in this method, you can't tell whether you are dealing with correct TBAA or not. Earlier, the discussion was basically &q...

...one will be released along with submission of my PhD thesis at the end > of the year. > > That said, if you are only looking for if-conversion of code with > limited complexity (e.g. no side effects, no loops), it is really simple: > - Compute masks for every block (entry mask: disjunction of incoming > masks, exit masks: conjunctions of entry mask and (negated) condition). > - Replace each phi by a select that uses the entry mask of the > corresponding block. > - Order blocks topologically by data dependencies, remove outgoing > edges, create unconditional bra...

.... LV: Can't vectorize due to memory conflicts LV: Not vectorizing. I asked this a few days ago; now it comes up again: Is there a way to qualify a pointer/Value to be 'restrict'? Another possible solution would be telling the loop vectorizer that it's safe to treat all arrays as disjunct. Is this possible? Frank On 28/10/13 15:11, Hal Finkel wrote: > ----- Original Message ----- >> I am trying to vectorize the function >> >> void bar(float *c, float *a, float *b) >> { >> const int width = 256; >> for (int i = 0 ; i < 256 ; ++i...

...'? Currently, no. There will be work in that direction soon. You'll need to extract a sub-function so that you can put 'noalias' on the function arguments. > > Another possible solution would be telling the loop vectorizer that > it's > safe to treat all arrays as disjunct. Is this possible? Yes. Look for llvm.mem.parallel_loop_access in the language reference. -Hal > > Frank > > > > > On 28/10/13 15:11, Hal Finkel wrote: > > ----- Original Message ----- > >> I am trying to vectorize the function > >> > >&gt...

...rrently, no. There will be work in that direction soon. You'll need to extract a sub-function so that you can put 'noalias' on the function arguments. > >> Another possible solution would be telling the loop vectorizer that >> it's >> safe to treat all arrays as disjunct. Is this possible? > Yes. Look for llvm.mem.parallel_loop_access in the language reference. > > -Hal > >> Frank >> >> >> >> >> On 28/10/13 15:11, Hal Finkel wrote: >>> ----- Original Message ----- >>>> I am trying to vectorize t...

...t the >>> end >>> of the year. >>> >>> That said, if you are only looking for if-conversion of code with >>> limited complexity (e.g. no side effects, no loops), it is really >>> simple: >>> - Compute masks for every block (entry mask: disjunction of >>> incoming >>> masks, exit masks: conjunctions of entry mask and (negated) >>> condition). >>> - Replace each phi by a select that uses the entry mask of the >>> corresponding block. >>> - Order blocks topologically by data dependencies,...

...he following instructions: 272L %vreg67:lo<def> = mv_any16 65535; R:%vreg67 288L %vreg64:hi<def> = mv_any16 16383; R:%vreg64 304L %vreg64:lo<def> = COPY %vreg67:lo; R:%vreg64,%vreg67 320L %vreg6<def> = COPY %vreg64<kill>; R:%vreg6,%vreg64 So, %vreg64, which has two (disjunct) sub registers, gets its two parts written at 288 and 304, and then the whole %vreg64 is copied to %vreg6 at 320. And for this I get the following intervals for %vreg64: %vreg64 = [288d,304d:1)[304d,320d:0) 0 at 304d 1 at 288d Later %vreg6 and %vreg64 are merged. The register allocator spil...