Displaying 7 results from an estimated 7 matches for "disablehazardrecogn".
2013 Sep 22
2
[LLVMdev] how to detect data hazard in pre-RA-sched
hi, LLVM,
I found there is a flag DisableHazardRecognizer in TargetInstrImpl.cpp. I
still don't understand how llvm detects data hazard in pre-RA-sched.
pre-RA-sched is based on SDNode and all operands are vregs. Even you can
calculate the operators of SDNodes, the data hazard in vreg are not same as
physical register data hazard. Is it useful to...
2013 Sep 24
0
[LLVMdev] how to detect data hazard in pre-RA-sched
On Sep 21, 2013, at 8:02 PM, Liu Xin <navy.xliu at gmail.com> wrote:
> hi, LLVM,
>
> I found there is a flag DisableHazardRecognizer in TargetInstrImpl.cpp. I still don't understand how llvm detects data hazard in pre-RA-sched. pre-RA-sched is based on SDNode and all operands are vregs. Even you can calculate the operators of SDNodes, the data hazard in vreg are not same as physical register data hazard. Is it useful to...
2013 Sep 25
2
[LLVMdev] how to detect data hazard in pre-RA-sched
...hat you want to balance register pressure and ILP in
misched.
On Tue, Sep 24, 2013 at 4:07 PM, Andrew Trick <atrick at apple.com> wrote:
>
> On Sep 21, 2013, at 8:02 PM, Liu Xin <navy.xliu at gmail.com> wrote:
>
> > hi, LLVM,
> >
> > I found there is a flag DisableHazardRecognizer in TargetInstrImpl.cpp.
> I still don't understand how llvm detects data hazard in pre-RA-sched.
> pre-RA-sched is based on SDNode and all operands are vregs. Even you can
> calculate the operators of SDNodes, the data hazard in vreg are not same as
> physical register data haza...
2013 Sep 25
0
[LLVMdev] how to detect data hazard in pre-RA-sched
...em, but it should never do anything too terrible either.
> On Tue, Sep 24, 2013 at 4:07 PM, Andrew Trick <atrick at apple.com> wrote:
>
> On Sep 21, 2013, at 8:02 PM, Liu Xin <navy.xliu at gmail.com> wrote:
>
> > hi, LLVM,
> >
> > I found there is a flag DisableHazardRecognizer in TargetInstrImpl.cpp. I still don't understand how llvm detects data hazard in pre-RA-sched. pre-RA-sched is based on SDNode and all operands are vregs. Even you can calculate the operators of SDNodes, the data hazard in vreg are not same as physical register data hazard. Is it useful to...
2013 Sep 26
2
[LLVMdev] how to detect data hazard in pre-RA-sched
...d both pre-RA and post-RA, right?
On Tue, Sep 24, 2013 at 4:07 PM, Andrew Trick <atrick at apple.com> wrote:
>
>>
>> On Sep 21, 2013, at 8:02 PM, Liu Xin <navy.xliu at gmail.com> wrote:
>>
>> > hi, LLVM,
>> >
>> > I found there is a flag DisableHazardRecognizer in TargetInstrImpl.cpp.
>> I still don't understand how llvm detects data hazard in pre-RA-sched.
>> pre-RA-sched is based on SDNode and all operands are vregs. Even you can
>> calculate the operators of SDNodes, the data hazard in vreg are not same as
>> physical re...
2013 Sep 26
0
[LLVMdev] how to detect data hazard in pre-RA-sched
...you're developing?
>
>> On Tue, Sep 24, 2013 at 4:07 PM, Andrew Trick <atrick at apple.com> wrote:
>>
>> On Sep 21, 2013, at 8:02 PM, Liu Xin <navy.xliu at gmail.com> wrote:
>>
>> > hi, LLVM,
>> >
>> > I found there is a flag DisableHazardRecognizer in TargetInstrImpl.cpp. I still don't understand how llvm detects data hazard in pre-RA-sched. pre-RA-sched is based on SDNode and all operands are vregs. Even you can calculate the operators of SDNodes, the data hazard in vreg are not same as physical register data hazard. Is it useful to...
2017 Jun 21
6
RFC: Cleaning up the Itanium demangler
...olorWithRegsOpt"},
{"_ZL8DCELimit", "DCELimit"},
{"_ZL17TailDuplicateSize", "TailDuplicateSize"},
{"_ZL13TailDupVerify", "TailDupVerify"},
{"_ZL12TailDupLimit", "TailDupLimit"},
{"_ZL23DisableHazardRecognizer", "DisableHazardRecognizer"},
{"_ZL11RewriterOpt", "RewriterOpt"},
{"_ZL14ScheduleSpills", "ScheduleSpills"},
{"_ZL17CriticalEdgeSplit", "CriticalEdgeSplit"},
{"_ZL9EnablePRE", "EnableP...