Displaying 3 results from an estimated 3 matches for "disableencoding".
2015 Nov 24
2
[backend]two-address encoding in llvm tblgen
...OpcodeStr, list<dag> Pattern>
> : InstV<(outs GPR:$rd), (ins GPR:$rdi, GPR:$rs), !strconcat(OpcodeStr,
> "\t$rd, $rs"), Pattern> {
> bits<5> rd;
> bits<6> rs;
> let Opcode=Op;
>
> let Constraints = "$rdi = $rd";
> let DisableEncoding = "$rdi";
> }
>
> -Hal
>
>>
>> It complains for 'rd'. I was wondering if there is any standard way
>> of
>> doing this?
>>
>> Thanks,
>> Xiaochu
>> _______________________________________________
>> LLVM Developers...
2015 Nov 24
2
[backend]two-address encoding in llvm tblgen
Dear there,
I'm developing an instruction layout like:
opcode | rd| ts
and its semantics is:
rd= rd opcode rs
But when I describe it in td file like this:
class R<bits<5> Op, string OpcodeStr, list<dag> Pattern>
: InstV<(outs GPR:$rd), (ins GPR:$rd, GPR:$rs), !strconcat(OpcodeStr,
"\t$rd, $rs"), Pattern> {
bits<5> rd;
bits<6> rs;
let
2013 Oct 03
0
[LLVMdev] Question about PseudoInstExpansion
...doMFHI GPR32:$rd, ACC64:$ac -> MFHI GPR32:$rd
Is there a way to tell the assembler, disassembler and instprinter to
ignore the ACC64:$ac operand? I know I can use PseudoInstExpansion to
accomplish this, but I just thought it would be convenient to have a flag
for this, something like flag "DisableEncoding". ACC64:$ac is just an
artificial operand added to create a virtual register live range.
Also, the code in utils/TableGen/PseudoLoweringEmitter.cpp (near line 141)
doesn't seem to allow converting a pseudo to a code-gen-only instruction.
What is the reason for this? Table-gen complains if...