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+Ahmed > On Mar 2, 2018, at 6:42 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com> wrote: > > There are a number of people on llvm-dev who can explain better than I how to decompile into MachineInstrs. I’m not totally opposed to checking in something that works with MCInstr, but this does run strongly contrary to the design of LLVM’s subtarget support. &gt...

...wards remodeling the code/datastructures to make reuse in llvm-mca simpler where it makes sense. - Matthias > On Mar 2, 2018, at 9:33 AM, Andrew Trick via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > +Ahmed > >> On Mar 2, 2018, at 6:42 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com <mailto:andrea.dibiagio at gmail.com>> wrote: >> >> There are a number of people on llvm-dev who can explain better than I how to decompile into MachineInstrs. I’m not totally opposed to checking in something that works with MCInstr, but this does run strongly con...

On Tue, Sep 9, 2014 at 11:39 PM, Chandler Carruth <chandlerc at google.com> wrote: > Awesome, thanks for all the information! > > See below: > > On Tue, Sep 9, 2014 at 6:13 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com> > wrote: >> >> You have already mentioned how the new shuffle lowering is missing >> some features; for example, you explicitly said that we currently lack >> of SSE4.1 blend support. Unfortunately, this seems to be one of the >> main reasons for th...

Hi Andrea, So does this definition make sense for basic blocks with more than one instructions? E.g. how should one interpret a basic block with RThroughput of 2.3? On Fri, Jun 7, 2019 at 7:39 AM Andrea Di Biagio <andrea.dibiagio at gmail.com> wrote: > Hi Tom, > > Field 'Total Cycles' from the summary view simply reports the elapsed > number of cycles for the entire simulation. > > Rthroughput (from the "Instruction Info" view) is the reciprocal of the > instruction throughput. &gt...

+Matthias > On Mar 2, 2018, at 6:42 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com> wrote: > >> Known limitations on X86 processors >> ----------------------------------- >> >> 1) Partial register updates versus full register updates. >> <snip> > > MachineOperand handles this. You just need to create the machine inst...

Hi Chandler, I have tested the new shuffle lowering on a AMD Jaguar cpu (which is AVX but not AVX2). On this particular target, there is a delay when output data from an execution unit is used as input to another execution unit of a different cluster. For example, There are 6 executions units which are divided into 3 execution clusters of Float(FPM,FPA), Vector Integer (MMXA,MMXB,IMM), and Store

I ran the benchmarking subset of test-suite on a btver2 machine and optimizing for btver2 (so enabling AVX codegen). I don't see anything outside of the noise with x86-experimental-vector-shuffle-legality=1. On Fri, Jan 23, 2015 at 5:19 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com > wrote: > Hi Chandler, > > On Fri, Jan 23, 2015 at 8:15 AM, Chandler Carruth <chandlerc at gmail.com> > wrote: > > Greetings LLVM hackers and x86 vector shufflers! > > > > I would like to flip on another chunk of the new vector shuffling, > &...

Andrea, thanks for the advice. On Jan 2, 2020, at 8:09 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com<mailto:andrea.dibiagio at gmail.com>> wrote: Hi Lewis, Basically - if I understand correctly - you want to design a pass that uses llvm-mca as a library to compute throughput indicators for your outlined functions. You would then use those indicators to classify outlined fun...

Wow. Somehow, I forgot about vbroadcast and vpbroadcast. =[ Sorry about that. I'll fix those. On Fri, Sep 26, 2014 at 3:39 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com > wrote: > Hi Chandler, > > Here is another test. > > When looking at the AVX codegen, I noticed that, when using the new > shuffle lowering, we no longer emit a single vbroadcastss in the case > where the shuffle performs a splat of a scalar float loaded from...

> On May 11, 2018, at 4:26 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com> wrote: > > The goal is to help users defining a predicate the check logic. If we use a TIIPredicate, we specify the logic only once, in a declarative way, and then we let tablegen generate code for us. > > If for some reason, a user doesn't want to use this approa...

> On Mar 6, 2018, at 4:20 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com> wrote: > > To be clear then, resolveSchedClass should be moved from TargetSchedModel into MCSchedModel (which is where I originally wanted it). Any TargetInstrInfo APIs called from SchedPredicate should be moved to MCInstrInfo, which should be straightforward but annoying. &...

...been willing to do this for quite some time now. Looks like procrastination was the right approach here ;). > On Mar 2, 2018, at 9:33 AM, Andrew Trick via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > +Ahmed > >> On Mar 2, 2018, at 6:42 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com <mailto:andrea.dibiagio at gmail.com>> wrote: >> >> There are a number of people on llvm-dev who can explain better than I how to decompile into MachineInstrs. I’m not totally opposed to checking in something that works with MCInstr, but this does run strongly con...

Hi Sjoerd, On Fri, May 3, 2019 at 8:19 AM Sjoerd Meijer via llvm-dev < llvm-dev at lists.llvm.org> wrote: > > I read that out-of-order cores are supported. How about in-order cores? > Would it be easy/difficult to add support for that? > > Cheers, > Sjoerd. > > I don't think that it would be difficult to support in-order superscalar cores. However, it would

> On Sep 9, 2014, at 3:39 PM, Chandler Carruth <chandlerc at google.com> wrote: > > Awesome, thanks for all the information! > > See below: > > On Tue, Sep 9, 2014 at 6:13 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com <mailto:andrea.dibiagio at gmail.com>> wrote: > You have already mentioned how the new shuffle lowering is missing > some features; for example, you explicitly said that we currently lack > of SSE4.1 blend support. Unfortunately, this seems to be one of the > main...

----- Original Message ----- > From: "Andrea Di Biagio" <andrea.dibiagio at gmail.com> > To: "Paul Robinson" <paul.robinson at sony.com> > Cc: "Hal Finkel" <hfinkel at anl.gov>, "David Blaikie" > <dblaikie at gmail.com>, llvm-dev at lists.llvm.org > Sent: Thursday, December 15, 2016 9:05:00 AM > Subject:...

Hi Andrew, Thanks for the feedback! On Fri, Mar 2, 2018 at 1:16 AM, Andrew Trick <atrick at apple.com> wrote: > > On Mar 1, 2018, at 9:22 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com> > wrote: > > Hi all, > > At Sony we developed an LLVM based performance analysis tool named > llvm-mca. We > currently use it internally to statically measure the performance of code, > and > to help triage potential problems with target scheduling models...

On Tue, Mar 6, 2018 at 5:55 AM, Andrew Trick via llvm-dev < llvm-dev at lists.llvm.org> wrote: > > > On Mar 5, 2018, at 6:28 PM, Matthias Braun <mbraun at apple.com> wrote: > > > > On Mar 5, 2018, at 6:14 PM, Andrew Trick via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > > On Mar 5, 2018, at 3:38 PM, Quentin Colombet <qcolombet at

...introduce a dominance check if/when we lift the one-basic-block >>>> restriction. >>>> >>>> -Matt >>>> >>>>> -Andrea >>>>> >>>>> On Tue, Nov 27, 2018 at 5:08 PM Andrea Di Biagio < >>>> andrea.dibiagio at gmail.com> >>>>> wrote: >>>>> >>>>>> Thanks for clarifying it Matt. >>>>>> >>>>>> In general, I quite like your suggested design. >>>>>> >>>>>> My only concern is about the...

...: * in test/Sema: ** Verify that noopt only applies to functions. (-cc1 -fsyntax-only -verify) * in test/CodeGen: ** Check that noopt implies noinline ** Check combinations of noopt and noinline and always_inline Andrea Di Biagio SN Systems - Sony Computer Entertainment Group. Andrea DiBiagio/SN R&D/BS/UK/SCEE wrote on 25/06/2013 15:20:12: > From: Andrea DiBiagio/SN R&D/BS/UK/SCEE > To: Nick Lewycky <nicholas at mxc.ca> > Cc: cfe-dev at cs.uiuc.edu, llvmdev at cs.uiuc.edu > Date: 25/06/2013 15:20 > Subject: Re: [LLVMdev] [RFC] add Function Attribute to disa...

...n remove this constraint. > > -Matt > > > -----Original Message----- > > From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Matt > Davis via llvm- > > dev > > Sent: Wednesday, November 21, 2018 8:47 AM > > To: Andrea Di Biagio <andrea.dibiagio at gmail.com> > > Cc: llvm-dev <llvm-dev at lists.llvm.org>; Di Biagio, Andrea > > <Andrea.Dibiagio at sony.com>; cfe-dev at lists.llvm.org > > Subject: Re: [llvm-dev] [RFC][llvm-mca] Adding binary support to > llvm-mca. > > > > Hi Andrea, > > &...