Displaying 3 results from an estimated 3 matches for "dfpregsregclass".
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fpregsregclass
2016 Mar 22
1
[cfe-dev] PATCH: clang/LLVM - Sparc - inline ASM with floating pointer registers
Your change looks almost correct.
You need:
- Test cases.
- Add the new 'f' type to the documentation in LangRef.rst.
- Check the type of the arg (f32, f64, or f128) to choose the right one of
FPRegsRegClass, DFPRegsRegClass, QFPRegsRegClass.
Then, please submit for review, per
http://llvm.org/docs/DeveloperPolicy.html
(Typically best to do so via Phabricator,
http://llvm.org/docs/Phabricator.html)
On Mon, Mar 21, 2016 at 6:46 PM, Arnaud Allard de Grandmaison via llvm-dev <
llvm-dev at lists.llvm.org> wrote:...
2016 Mar 21
0
[cfe-dev] PATCH: clang/LLVM - Sparc - inline ASM with floating pointer registers
Hi Patrick,
I do not see a problem with those patches --- apart from missing tests ;)
Cheers,
Arnaud
On Mon, Mar 21, 2016 at 3:11 PM, Patrick Boettcher via cfe-dev <
cfe-dev at lists.llvm.org> wrote:
> Hi lists,
>
> Sorry for cross-posting, but these two patches are of concern to clang
> and llvm.
>
> I'm compiling C-code which includes inline assembler which looks
2016 Mar 21
2
PATCH: clang/LLVM - Sparc - inline ASM with floating pointer registers
Hi lists,
Sorry for cross-posting, but these two patches are of concern to clang
and llvm.
I'm compiling C-code which includes inline assembler which looks like
the following using the sparc-target:
static inline float fabsf(float a)
{
float res;
__asm __volatile__("fabss %1, %0;"
: "=f"(res)
: "f"(a));
return