search for: dfapacketizer

...lcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation *From:*llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] *On Behalf Of *Jonas Paulsson *Sent:* Monday, February 11, 2013 11:16 AM *To:* llvmdev at cs.uiuc.edu *Subject:* [LLVMdev] DFAPacketizer Hi, I am having problems writing the ProcessorItineraries list. As instructions on my VLIW target have varying size I want to model both cpu units and bundle bits as FUs. The following does not work, to my surprise: InstrItinData<ALU, [InstrStage<1, [BITS1,BITS2, BITS3, BITS4], 0>,...

Hi, I'm trying to get the DFAPacketizer to work for my target but with any instruction I get the 'Assertion `CachedTable.count(StateTrans) != 0' failed' error and it crashes out before packeting a single instruction. I have a *GenDFAPacketizer.inc file and my packetizer pass checks that the table is not empty before proceed...

...Hi, > > I looked a bit through the mail archives, and found this question > answered in Oct 2011 (see below). It is interesting to find this in > the ARM backend, considering your answer. Can you give more > information about for example is this a temporary deficiency in the > DFAPacketizer? What is the IIC_iMOVi itinerary doing below? > > Thanks, > > Jonas > > /Thu Oct 6 15:11:25 CDT 2011:/ > > // > > /Hello Hal./ > > // > > /> Is there a way to express a multiple pipeline itinerary using the/ > > /> current scheme/ > > /Yes...

...resources for the first instruction, or any of my instructions for that matter. Have you ever seen this problem before? thanks sam On 12/06/12 15:48, Ivan Llopard [via LLVM] wrote: > Hi Sam, > > On 12/06/2012 15:33, sam wrote: > > Hi, > > > > I'm trying to get the DFAPacketizer to work for my target but with any > > instruction I get the > > 'Assertion `CachedTable.count(StateTrans) != 0' failed' error and it > crashes > > out before packeting a single instruction. > > Do you reserve some resource without verification? > > Not...

Hi, I looked a bit through the mail archives, and found this question answered in Oct 2011 (see below). It is interesting to find this in the ARM backend, considering your answer. Can you give more information about for example is this a temporary deficiency in the DFAPacketizer? What is the IIC_iMOVi itinerary doing below? Thanks, Jonas Thu Oct 6 15:11:25 CDT 2011: Hello Hal. > Is there a way to express a multiple pipeline itinerary using the > current scheme Yes, surely > (maybe some trick with setting NextCycles = 0)? Yep! > Specifically, consider a...

...tilisation. Does your first instruction have an defined itinerary? Ivan > > thanks > sam > > On 12/06/12 15:48, Ivan Llopard [via LLVM] wrote: >> Hi Sam, >> >> On 12/06/2012 15:33, sam wrote: >> > Hi, >> > >> > I'm trying to get the DFAPacketizer to work for my target but with any >> > instruction I get the >> > 'Assertion `CachedTable.count(StateTrans) != 0' failed' error and >> it crashes >> > out before packeting a single instruction. >> >> Do you reserve some resource without ver...

...... ie handle multiple stages ? I might do it and commit, if there is acceptance and guidance... Jonas ________________________________ From: Anshuman Dasgupta [mailto:adasgupt at codeaurora.org] Sent: Tuesday, February 12, 2013 4:47 PM To: Jonas Paulsson Cc: llvmdev at cs.uiuc.edu Subject: Re: DFAPacketizer Hi Jonas, > It is interesting to find this in the ARM backend, considering your answer. The ARM backend doesn't use the DFA packetizer. It's only used by Hexagon. At this point, there is no plan to address this in the DFA packetizer since none of the supported targets need the functio...

Hi Sam, On 12/06/2012 15:33, sam wrote: > Hi, > > I'm trying to get the DFAPacketizer to work for my target but with any > instruction I get the > 'Assertion `CachedTable.count(StateTrans) != 0' failed' error and it crashes > out before packeting a single instruction. Do you reserve some resource without verification? Note that reserveResources() should be cal...

...h64 + Scalable Vector Extension environment. MachinePipeliner is currently used only by Hexagon CPU. Since it is a very portable implementation, I think that it will actually work just by adding a little code for many CPUs(See Code [2]). The current MachinePipeliner is written on the premise that DFAPacketizer is used for resource management. However, I'd like to use MachinePipeliner in a way that does not use DFAPacketizer for the reasons described below(*). In MachinePipeliner implementation, only a small part is dependent on DFAPacketizer or Instruction itineraries. Therefore, I think that one of...

Hi all, I have found what I think it is a bug in DFAPacketizer::ReadTable. When finding NextStateInTable to cache all transitions belonging to a state into CachedTable, ReadTable does not check bounds: unsigned ThisState = DFAStateEntryTable[state]; | unsigned NextStateInTable = DFAStateEntryTable[state+1]; which makes NextStateInTable get a random value wh...

...I'll confirm and fix. Is there a bug report open for this? -Anshu --- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation On 12/10/2012 4:48 AM, Carlos Sánchez de La Lama wrote: > Hi all, > > I have found what I think it is a bug in DFAPacketizer::ReadTable. > > When finding NextStateInTable to cache all transitions belonging to a > state into CachedTable, ReadTable does not check bounds: > > unsigned ThisState = DFAStateEntryTable[state]; | > unsigned NextStateInTable = DFAStateEntryTable[state+1]; > > which makes...

Hi Anshu, no, I did not fill a bug report. It is not so easy to make the code fail noticeably; during Hexagon CodeGen tests it happens silently and tests pass. I am working on another VLIW backend which uses DFAPacketizer and compiling llvm with gcc-4.4 makes it segfault, but with gcc-4.7 the bug gets hidden again (it still happens, but values after DFAStateEntryTable in memory are such that ReadTable does not break bad). If you find more info will help you track it down just let me know :) BR Carlos 2012/12/10...

...pe of instructions several times, I would like to be allowed only two such instructions per cycle. ResourceTracker->reserveResources(); ResourceTracker->reserveResources(); ResourceTracker->reserveResources(); ResourceTracker->reserveResources(); ResourceTracker->reserveResources(); DFAPacketizer.cpp:84: void llvm::DFAPacketizer::reserveResources(const llvm::MCInstrDesc*): Assertion `CachedTable.count(StateTrans) != 0' failed. It seems to not want to worry about the alu's, but it is fine as long as there are any FU of the first row (BITS) available. What is missing? Thanks, Jona...

For some reason on my VLIW target DFAPacketizer fails at assert(CachedTable.count(StateTrans) != 0); in the following function: // reserveResources - Reserve the resources occupied by a MCInstrDesc and // change the current state to reflect that change. void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) { unsigned InsnClass...

...On 12/10/2012 1:01 PM, Carlos Sánchez de La Lama wrote: > Hi Anshu, > > no, I did not fill a bug report. It is not so easy to make the code > fail noticeably; during Hexagon CodeGen tests it happens silently and > tests pass. I am working on another VLIW backend which uses > DFAPacketizer and compiling llvm with gcc-4.4 makes it segfault, but > with gcc-4.7 the bug gets hidden again (it still happens, but values > after DFAStateEntryTable in memory are such that ReadTable does not > break bad). > > If you find more info will help you track it down just let me know...

> Does the instruction that is being added have an itinerary associated with > it? > So I checked again, and it turns out that it does have an itinerary associated with it. However it is a pseudo instruction. Does the packetizer do something special with the pseudo instructions? I didn't see any special code, but I could have missed it. -- R -------------- next part --------------

...> On 12/10/2012 1:01 PM, Carlos Sánchez de La Lama wrote: > > Hi Anshu, > > no, I did not fill a bug report. It is not so easy to make the code fail > noticeably; during Hexagon CodeGen tests it happens silently and tests > pass. I am working on another VLIW backend which uses DFAPacketizer and > compiling llvm with gcc-4.4 makes it segfault, but with gcc-4.7 the bug > gets hidden again (it still happens, but values after DFAStateEntryTable in > memory are such that ReadTable does not break bad). > > If you find more info will help you track it down just let me know :)...

...PM, Carlos Sánchez de La Lama wrote: >> >> Hi Anshu, >> >> no, I did not fill a bug report. It is not so easy to make the code >> fail noticeably; during Hexagon CodeGen tests it happens silently and tests >> pass. I am working on another VLIW backend which uses DFAPacketizer and >> compiling llvm with gcc-4.4 makes it segfault, but with gcc-4.7 the bug >> gets hidden again (it still happens, but values after DFAStateEntryTable in >> memory are such that ReadTable does not break bad). >> >> If you find more info will help you track it down...

I'm unclear how does DFAPacketizer and the scheduler know a given instruction is a load. Here is what I'm talking about Let's assume my VLIW target is described as follows: def MyTargetItineraries : ProcessorItineraries<[Slot0, Slot1], [], [ .............................. InstrItinData<RI, [Inst...

In the Hexagon backend we originally treated CFI instructions as "solo", > i.e. they could not be packetized with any other instruction. Now we > simply delay the generation of these instructions until after > packetization. The reason for this is that two instructions that could be > packetized together were not packetized together if there was an CFI > instruction in