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...s into other sequences, but I'm unsure how I can get an input in the correct format to construct a good unit test. Can I generate an ".ll" file using target specific instructions and then pass it through to a back-end MachineFunctionPass to test specifically just that one pass? Chris Dewhurst, Lero, University of Limerick. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160801/e78b3cc6/attachment.html>

...h the simple "assembler-only support" recommended below, unless anyone can recommend a simple way of achieving the above (and direct me to a suitable reference). I can't find anything sufficiently similar in any of the other processors supported by LLVM. Thanks for the feedback Chris Dewhurst University of Limerick. ________________________________ From: James Y Knight [jyknight at google.com] Sent: 18 September 2015 16:39 To: Chris.Dewhurst Cc: llvm-dev at lists.llvm.org Subject: Re: [llvm-dev] multiply-accumulate instruction Do you only want to define assembler syntax for this, or do...

..., (add i32:$asr18, (mul i32:$rs1, i32:$rs2)))] >; Perhaps a well-chosen "let Constraints=" might be used here? If so, I'm not sure I know what to put in there. If not, can anyone help me how I might define the lowering rules for this instruction please? Chris Dewhurst, University of Limerick. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150918/9c2df28c/attachment.html>

...ildMI(MBB, MBBI, DL, TII.get(SP::FSTOD), MO.getReg()); [ Then we'd do the second fstod and the fmuld, but I've not included this because the basic problem of generating the MachineInstr has happened already for this first MachineInstr] MI.eraseFromParent(); } Chris Dewhurst, University of Limerick, Ireland -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150908/f5a1ce0b/attachment.html>

...ies. I can provide more details on specifics, but rather than head off into excessive details immediately, I'd appreciate if anyone can help me identify what direction I really should be taking to fix this problem. I'm not convinced I've been going about it the right way so far. Chris Dewhurst, Lero, University of Limerick. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20161019/6e832839/attachment.html>

...lse in Sparc. I imagine this is similar if I try to make a CALLRi or CALLrr call, but looking through the code there isn't yielding any obvious solution to me. Would anyone be able to point me at a relevant piece of code that can do this, or is already doing it for Sparc? Best Regards, Chris Dewhurst / Lero, University of Limerick, Ireland. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160415/43d52775/attachment.html>

...ors. I'd prefer to do the first of these and get the vectors represented as registers. This seems more efficient. Any help pointing me in the right direction will be greatly appreciated. I don't suppose there's anything as simple a a clang command-line flag that will do this??? Chris Dewhurst, LERO, The Irish Software Research Centre, University of Limerick. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160128/fea79406/attachment.html>

...ot;note about autoconf build having been removed". Do you want to expand this? :-) - Danny, George: do you want to add something about MemorySSA? - Nico, do you want to mention clang-cl's precompiled header support? - James, do you want to mention the removal of the CppBackend? - Chris Dewhurst, do you want to mention soft-float SPARC support (and potentially other SPARC improvements)? - Benjamin, should we mention include-fixer somewhere? Many thanks, Hans [1] http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/docs/ReleaseNotes.rst?view=markup

Hi, in section B.29. (Write State Register Instructions) of 'The SPARC Architecture Manual Version 8' it is said that the "The write state register instructions are delayed-write instructions." The Y-register is a state-register. Furthermore in the B.29-secion there is a programming note saying: MULScc, RDY, SDIV, SDIVcc, UDIV, and UDIVcc implicitly read the Y register.

Hi, I'm implementing __builtin_setjmp and __builtin_longjmp for Sparc 32 bit processors (64 bit later, time allowing). I'm basing the code on the PowerPC version, which itself is based on the X86 version. This code is very nearly working, and I've had it working for -O0 optimisation (with a slightly different version to that below), so I know it's close. However, the PowerPC