search for: desugar

Displaying 20 results from an estimated 23 matches for "desugar".

2020 Mar 16
3
GSOC Projects
Hey, I am Swapnil Raj I am student in Trinity College Dublin and I am interested in working on LLVM. I am really interested in two projects listed, the first one is the extending the clang AST with template information and the second is finding smart null pointer dereferences. I am passionate about compilers and interpreters, I have written a few small language based on lambda calculus. I am
2014 May 26
3
[LLVMdev] Why can't atomic loads and stores handle floats?
...king hacks in the frontend. To say this differently, why should marking loads and stores atomic required me to rewrite largish chunks of code around the load or store? There's nothing "wrong" per se with that design, but why complicate a bunch of frontends when a single IR level desugarring pass could preform the same logic? Another answer would be that bitcasts make the IR less readable. They consume memory. Unless handled carefully, they inhibit optimizations. (i.e. if you forget to strip casts in a peephole optimization) When dealing with large IR files from a language w...
2012 Sep 26
0
[LLVMdev] [RFC] Parallelization metadata and intrinsics in LLVM (for OpenMP, etc.)
...of threads in the thread pool. It should be possible to lower all OpenMP directives to the above four intrinsics in the frontend (please read this in conjunction with [1]): Parallel regions can be lowered as a parallel_map with @llvm.num_threads as the limit. ``` #pragma PARALLEL block ``` desugars to ``` @llvm.parallel_map(num_threads, block_closure, shared_closure) ... void block_closure(i32 tid, i8* shared_vars) { block } ``` Reductions are handled by a parallel_map followed by a regular reduction loop (exactly as in Hal's proposal). Serial blocks reduce to a block conditional on...
2014 May 24
3
[LLVMdev] Why can't atomic loads and stores handle floats?
...lobal %"struct.std::atomic.2" zeroinitializer, align 4 define void @foo() { %1 = load atomic i32* bitcast (%"struct.std::atomic.2"* @aFloat to i32*) seq_cst, align 4 %2 = bitcast i32 %1 to float ... } This seems less than ideal. I would expect that we might have to desugar floats into integer & cast operations in the backend, but why is this imposed on the frontend? More generally, is there anyone who is knowledgeable and/or working on atomics and synchronization in LLVM? I've got a number of questions w.r.t. semantics and have found a number of what I b...
2012 Aug 14
4
[LLVMdev] [RFC] Parallelization metadata and intrinsics in LLVM (for OpenMP, etc.)
On Tue, 14 Aug 2012 10:22:35 +0300 Pekka Jääskeläinen <pekka.jaaskelainen at tut.fi> wrote: > On 08/13/2012 10:54 PM, Hal Finkel wrote: > > I had thought about uses for shared-memory OpenCL implementations, > > but I don't know enough about the use cases to make a specific > > proposal. Is your metadata documented anywhere? > > It is now a quick "brute
2012 Sep 26
1
[LLVMdev] [RFC] Parallelization metadata and intrinsics in LLVM (for OpenMP, etc.)
...of threads in the thread pool. It should be possible to lower all OpenMP directives to the above four intrinsics in the frontend (please read this in conjunction with [1]): Parallel regions can be lowered as a parallel_map with @llvm.num_threads as the limit. ``` #pragma PARALLEL block ``` desugars to ``` @llvm.parallel_map(num_threads, block_closure, shared_closure) ... void block_closure(i32 tid, i8* shared_vars) { block } ``` Reductions are handled by a parallel_map followed by a regular reduction loop (exactly as in Hal's proposal). Serial blocks reduce to a block conditional on...
2013 Oct 25
1
[LLVMdev] Interfacing llvm with a precise, relocating GC
...a of > how much work that would be and what the costs and benefits for LLVM > are. > > Also to note is that there are plans to move away from selection dag, > so it might be good to sync this work with whatever we end up using > instead. Ouch. I hadn't realized that GEPs were desugared to integer arithmetic that early. That does seem like it would be a problem. Thank you for pointing this out. Assuming we had a scheme to avoid/solve this specific issue, are you aware of any other ones? Can you point me to any previous discussion of the selection dag migration? This isn...
2013 Jan 02
0
[LLVMdev] [lld] Linker script findings.
Sean, Thanks for doing this research and writing up that summary! The SECTION and MEMORY seem doable in lld as part of the ELF Writer. The one tricky part will be if the linker script defines symbols (e.g. __text_size), because those symbol names might be referenced by some object file atom. Thus they need an atom representation for lld's Resolver to see. So, the ELF Writer will need
2017 Jan 03
2
Optimisation passes introducing address space casts
...n `addrspace(0)`) is then passed to a function. The test asserts that this memcpy should be removed and the global should just be passed directly to the function, but doesn’t this lose the property that the load should be performed through `addrspace(1)`, as per your comment above? > > Let’s desugarize memcpy to a sequence of load-store as my previous comment implied (simplified for a single i8, otherwise we need a loop or a load of T, but the reasoning seems the same to me): > > > define void @test3_addrspacecast() { > %A = alloca %T > %a = bitcast %T* %A to i8* &gt...
2013 Jan 03
2
[LLVMdev] [lld] Linker script findings.
...:53 PM, Nick Kledzik <kledzik at apple.com> wrote: > The SECTION and MEMORY seem doable in lld as part of the ELF > Writer. MEMORY and most aspects of SECTIONS are effectively syntax sugar and the rest of LLD doesn't need to even be aware of it; the ldscript language processor will desugar it. The same is true of many other linker script constructs that I didn't mention. The goal of the write-up was to describe the primitive functionality that will be needed at the boundary between the language processor and the rest of LLD (although admittedly some parts of the write-up still he...
2013 Oct 24
0
[LLVMdev] Interfacing llvm with a precise, relocating GC
On 24 October 2013 17:32, Sanjoy Das <sanjoy at azulsystems.com> wrote: > Hello llvm-dev! > > My colleages and I are currently evaluating llvm's suitability as a > JIT compiler interfacing with a precise, relocating garbage collector. > While we couldn't find code or writeups that deal with the issues > specific to this design goal, it is entirely possible that we
2012 Aug 02
0
[LLVMdev] Reading the output of clang
What is the best level to use for backend development? We do not need to generate machine code, but rather an intermediate representation that will give us the control flow graph. Is this the llvm IR? If so, how do I read into memory a file that was generated by clang++ -emit-llvm <source file>. Thanks, Sitvanit Sitvanit Ruah Formal Verification Group IBM Haifa Research Laboratory Tel:
2012 Aug 01
3
[LLVMdev] Reading the AST from the bitcode generated by clang
> Hi all, > After reading the documentation on clang I still have the following > question: > How do I read the bitcode generated by clang from a C++ file? I need to > have all the AST information in memory. AST has nothing to do with LLVM bitcode. -- Regards, Konstantin
2017 Jan 02
3
Optimisation passes introducing address space casts
Hi Mehdi, Thanks for the reply - I’ve finally got round to trying to fix this based on your suggestion. I’ve got something that mostly works, but I just wanted to double-check something about the regression tests before I post a patch. > The memcpy is supposed to be equivalent to a sequence of load and store. Here we are just failing to keep the property that the load is performed through
2013 Oct 24
5
[LLVMdev] Interfacing llvm with a precise, relocating GC
Hello llvm-dev! My colleages and I are currently evaluating llvm's suitability as a JIT compiler interfacing with a precise, relocating garbage collector. While we couldn't find code or writeups that deal with the issues specific to this design goal, it is entirely possible that we may have missed something; we would appreciate references to relevant code or writeups that people on this
2014 May 01
2
[LLVMdev] Proposal: add intrinsics for safe division
...uld be > great if you could get those semantics - along with a known-good > implementation - on other architectures as well. > I would be very interested in seeing data comparing two schemes: - Explicit control flow emited by the frontend - The safe.div intrinsic emitted by the frontend, desugared in CodeGenPrep My strong suspicion is that each would preform well in some cases and not in others. At least on x86. Since the edge-checks are essentially free on ARM, the second scheme would probably be strictly superior there. I am NOT asking that we block submission on this data however....
2012 Dec 31
5
[LLVMdev] [lld] Linker script findings.
Hi all, I have been investigating linker scripts and the functionality needed to support them in lld. I have attached my findings about the usage of ldscripts. My findings have been collected from: - Reading all the GNU ld manual sections about linker scripts. - Looking at the GNU ld and gold source code. - Digging through a couple embedded programming tutorials. - Reading through all of the
2014 May 02
3
[LLVMdev] Proposal: add intrinsics for safe division
...if you could get those semantics - along  > with a known-good implementation - on other architectures as well.  >  > I would be very interested in seeing data comparing two schemes:  > - Explicit control flow emited by the frontend  > - The safe.div intrinsic emitted by the frontend, desugared in CodeGenPrep  >  > My strong suspicion is that each would preform well in some cases and not in  > others. At least on x86. Since the edge-checks are essentially free on  > ARM, the second scheme would probably be strictly superior there.  >  > I am NOT asking that we block su...
2014 May 01
6
[LLVMdev] Proposal: add intrinsics for safe division
...emantics - along with a known-good >>> implementation - on other architectures as well. >>> >> I would be very interested in seeing data comparing two schemes: >> - Explicit control flow emited by the frontend >> - The safe.div intrinsic emitted by the frontend, desugared in >> CodeGenPrep >> >> My strong suspicion is that each would preform well in some cases and >> not in others. At least on x86. Since the edge-checks are >> essentially free on ARM, the second scheme would probably be strictly >> superior there. >>...
2017 Aug 01
7
[RFC] Add IR level interprocedural outliner for code size.
> > > > Also as a side note, I think in the original MachineOutliner RFC thread > there was some confusion as to whether it was possible to solve the code > folding outlining problem exactly as a graph problem on SSA using standard > value numbering algorithms in polynomial time. > > I can elaborate further, but > 1. it is easy to see that you can map an arbitrary