search for: destreg

...ed to take a register class enum value and get the register class object for it. It doesn't convert a register to a class. In fact there's not always a single or canonical class for a given register. What is the right way to do this? unsigned SrcReg = Reg + VA.getValNo(); unsigned DestReg = VA.getLocReg(); // Avoid a cross-class copy. This is very unlikely. if (!MRI.getRegClass(SrcReg)->contains(DestReg)) return false; ~Craig -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/201...

Hi, Paul Curtis wrote: > If you read the Arm Architecture document for ARMv5, it states for MUL: > > "Operand restriction: Specifying the same register for <Rd> and <Rm> was > previously described as producing UNPREDICTABLE results. There is no > restriction in ARMv6, and it is believed all relevant ARMv4 and ARMv5 > implementations do not require this

Hi, > I am using a cross compiler to compiler for the arm5 architecture. For this > architecture it is not allowed that a destination register is also used as source > register. > In 2007 a patch was discussed at the mailing list, however my compiler still is > producing this result. Does anyone know if this patch is actually applied? > > * I use the following arguments:

Hi, I am using a cross compiler to compiler for the arm5 architecture. For this architecture it is not allowed that a destination register is also used as source register. In 2007 a patch was discussed at the mailing list, however my compiler still is producing this result. Does anyone know if this patch is actually applied? * I use the following arguments: llvm-gcc -mfpu=vfp -mlittle-endian

...opy placement. For this setkill action it looks only in one instruction (last instruction for copyRegToReg) for virtual register with no use. My target has only one register and I can't do copyRegToReg in one instruction only. So I create two instructions (one:SrcReg to Stack , two:Stack to DestReg). The SrcReg here is the temporary virtual register (for PHI elimination) which should be setkill. However, the PHI Elimination pass looks only in last instruction (here: Stack to DestReg) for any NoUse register and does not find any. Therefore the intended setkill does not take place. This causes...

...perand::CreateReg(0)); } unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const { return 0; } void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const { - AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) - .addReg(SrcReg, getKillRegState(KillSrc))); + // Need to check the arch. + MachineFunction &MF = *MBB.getParent(); + const ARMSubtarget &st = MF...

...electInstructi > } > > unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) { > - int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); > - if (VT == MVT::f32) { > - const TargetRegisterClass *RC = &Mips::FGR32RegClass; > - unsigned DestReg = createResultReg(RC); > - unsigned TempReg = Materialize32BitInt(Imm, &Mips::GPR32RegClass); > - EmitInst(Mips::MTC1, DestReg).addReg(TempReg); > - return DestReg; > - } else if (VT == MVT::f64) { > - const TargetRegisterClass *RC = &Mips::AFGR64RegClass; > -...

Hi Bill, I am using the following version of BuildMI : MachineInstrBuilder BuildMI(MachineFunction &MF, const TargetInstrDesc &TID, unsigned DestReg) I do the following : void createInstrs(std::vector<MachineInstr *>& ilist) { Machine Instr *mi; mi = BuildMI(MF, someTID, somereg); ilist.push_back(mi); mi = BuildMI(MF, someotherTID, someotherreg); ilist.push_back(mi); } viud insertInto(MachineBasicBlock *BB, MachineBasicB...

...); BuildMI(MBB, MI, DL, get(Picoblaze::REGXXSTACKEND ));//.addMemOperand(MMO); ; MF.dump(); } void PicoblazeInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { PR_FUNCTION(); DebugLoc DL; if (MI != MBB.end()) DL = MI->getDebugLoc(); MachineFunction &MF = *MBB.getParent();...

...e getReg(*) methods in the X86 instruction selector. The basic code generation stage for an add, boiled down to its simplest form, basically looks like this: void visitAdd(BinaryOperator &B) { unsigned Op0Reg = getReg(B.getOperand(0)); unsigned Op1Reg = getReg(B.getOperand(1)); unsigned DestReg = getReg(B); unsigned Opcode = (get the opcode for the size of the add); BuildMI(<where>, Opcode, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg); } The nice thing about the "getReg" functionality is that it is a member of the instruction selector class, so it has the context to sto...

Ok, I'm now trying to write instruction selector and have some questions 1. The MachineInstrBuilder has methods to add register operand and immediate operand. However, what would be really nice is a method to add Value*. So, I would write: BuildMI(*BB, NM::add, 1).add(I.getOperand(0), I.getOperand(1)); and depending on whether the passed Value* is contant or instruction, the add

...const MCInstrDesc &MCID) { return BuildMI(*BB, BB->end(), DL, MCID); } inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, DebugLoc DL, const MCInstrDesc &MCID, unsigned DestReg) { return BuildMI(*BB, BB->end(), DL, MCID, DestReg); } -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Hi all, There's been a recent bootstrap failure that might be covered up because of another failure. I just wanted to point this out so that people can take a look: -bw Here's the failure from our buildbot: Assertion failed: (DestReg == VirtReg && "Unknown load situation!"), function RewriteMBB, file /Volumes/Sandbox/Buildbot/llvm/build.llvm- gcc-x86_64-darwin10-selfhost/llvmCore.roots/llvmCore~obj/src/lib/ CodeGen/VirtRegRewriter.cpp, line 2294. /Volumes/Sandbox/Buildbot/llvm/build.llvm-gcc-x86_64-darwin1...

...truction > selector. The basic code generation stage for an add, boiled down to its > simplest form, basically looks like this: > > void visitAdd(BinaryOperator &B) { > unsigned Op0Reg = getReg(B.getOperand(0)); > unsigned Op1Reg = getReg(B.getOperand(1)); > unsigned DestReg = getReg(B); > > unsigned Opcode = (get the opcode for the size of the add); > BuildMI(<where>, Opcode, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg); > } > > The nice thing about the "getReg" functionality is that it is a member of > the instruction selector cl...

I am seeing the following assertion in leak detector. /llvm/lib/VMCore/LeakDetector.cpp:43: void<unnamed>::LeakDetectorImpl<T>::addGarbage(const T*) [with T = void]: Assertion `Ts.count(Cache) == 0 && "Object already in set!"' failed. I am creating a list of instructions using BuildMI() and adding them to a basic block using BB->insert(). I am seeing this

On Wed, Jun 3, 2009 at 5:10 PM, Manjunath Kudlur <keveman at gmail.com> wrote: > I am seeing the following assertion in leak detector. > > /llvm/lib/VMCore/LeakDetector.cpp:43: > void<unnamed>::LeakDetectorImpl<T>::addGarbage(const T*) [with T = > void]: Assertion `Ts.count(Cache) == 0 && "Object already in set!"' > failed. > > I am

Chris Lattner wrote: > On Thu, 2 Dec 2004, Brent Monroe wrote: > >>I'm trying to add the xadd instruction to the X86 back end. >>xadd r/m32, r32 >>exchanges r/m32 and r32, and loads the sum into r/m32. I'm >>interested in the case where the destination operand is a >>memory location. >> >>I've added the following entry to

I am new to the LLVM backends, I am wondering how instruction selection is done in LLVM backends, I looked at the .td files in Target/X86, they all seem to be small and do not deal with common X86 instructions, i.e. mov, push, pop, etc. Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL:

...IndexReg + Disp32 In order to represent this, LLVM tracks no less than 5 operands for each memory operand of this form. This means that the “load” form of ‘mov’ has the following MachineOperands in this order: Index: 0 | 1 2 3 4 5 Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement Segment OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm PhysReg Stores, and all other instructions, treat the four memory operands in the same way and in the same order. If the segment register is unspecified (regno = 0), then no segme...

...ot be byte sized? I guess we'll worry about it if someone adds that target. :-) > > > /// TargetInstrInfoImpl - This is the default implementation of > @@ -408,6 +420,7 @@ > MachineBasicBlock::iterator MI, > unsigned DestReg, > const MachineInstr *Orig) const; > + virtual unsigned GetFunctionSize(const MachineFunction &MF) const; > }; > > } // End llvm namespace > Index: lib/CodeGen/TargetInstrInfoImpl.cpp > =========================================================...