Displaying 4 results from an estimated 4 matches for "destition".
2005 Jul 22
2
[LLVMdev] How to partition registers into different RegisterClass?
...RegisterClass<...>;
def WriteOnlyRegClass : RegisterClass<...>;
def MOV : BinaryInst<2, (ops GeneralPurposeRegClass :$dest,
GeneralPurposeRegClass :$src), "mov $dest, $src">;
There can be only one RegisterClass defined for each instruction
operand, but actually the destition operand could be
'GeneralPurposeRegClass ' or 'WriteOnlyRegClass ', and the source
operand can be 'ReadOnlyRegClass' or 'GeneralPurposeRegClass'.
--
Tzu-Chien Chiu
http://www.csie.nctu.edu.tw/~jwchiu/
2005 Jul 22
0
[LLVMdev] How to partition registers into different RegisterClass?
...that I can easy define the
> instruction?
[snip]
> def MOV : BinaryInst<2, (ops GeneralPurposeRegClass :$dest,
> GeneralPurposeRegClass :$src), "mov $dest, $src">;
>
> There can be only one RegisterClass defined for each instruction
> operand, but actually the destition operand could be
> 'GeneralPurposeRegClass ' or 'WriteOnlyRegClass ', and the source
> operand can be 'ReadOnlyRegClass' or 'GeneralPurposeRegClass'.
Presumably, when you write your instruction selector, you know when you
want to have a write-only vs. general...
2005 Jul 22
2
[LLVMdev] How to partition registers into different RegisterClass?
...t; instruction?
> [snip]
> > def MOV : BinaryInst<2, (ops GeneralPurposeRegClass :$dest,
> > GeneralPurposeRegClass :$src), "mov $dest, $src">;
> >
> > There can be only one RegisterClass defined for each instruction
> > operand, but actually the destition operand could be
> > 'GeneralPurposeRegClass ' or 'WriteOnlyRegClass ', and the source
> > operand can be 'ReadOnlyRegClass' or 'GeneralPurposeRegClass'.
>
> Presumably, when you write your instruction selector, you know when you
> want to have...
2005 Jul 22
0
[LLVMdev] How to partition registers into different RegisterClass?
...;> [snip]
>>> def MOV : BinaryInst<2, (ops GeneralPurposeRegClass :$dest,
>>> GeneralPurposeRegClass :$src), "mov $dest, $src">;
>>>
>>> There can be only one RegisterClass defined for each instruction
>>> operand, but actually the destition operand could be
>>> 'GeneralPurposeRegClass ' or 'WriteOnlyRegClass ', and the source
>>> operand can be 'ReadOnlyRegClass' or 'GeneralPurposeRegClass'.
>>
>> Presumably, when you write your instruction selector, you know when you
>&...