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Hi, In my target, certain intrinsic functions read or write the machine's flag registers. Some of my benchmarks rely on implicit data dependences among such intrinsics. How can I specify that these intrinsics carry this dependence, and that this dependence should be preserved through instruction selection? For example, suppose I have this snippet of IR: ; (i) Write to flags tail call

Hello, While tuning the MIScheduler for my target, I discovered a code that unnecessarily restricts the scheduler. I think this is a bug, but I would appreciate a second opinion. In file ScheduleDAGInstrs.cpp, the function MIsNeedChainEdge determines whether two MachineInstrs are ordered by a memory dependence. It first runs through the standard criteria (Do both instructions access memory?