search for: descripiton

...he Codegen infrastructure, ARMInstrInfo.td file has complete description of the instructions which modify the status flags. For example, we have description for both ADD and ADDS. But the problem is that in LLVM, we have a single "ADD" Instruction. Thus when we do getDesc(add), we get the descripiton corresponding to "ADD". When I was reading the code, I got a feeling that if we are able to modify this selection of "ADD" to "ADDS"( provided we somehow determine that we need ADDS here), then everything else related to ARM instruction generation has been handled in c...

...RMInstrInfo.td file has complete description of the instructions > which modify the status flags. For example, we have description for > both ADD and ADDS. But the problem is that in LLVM, we have a single > "ADD" Instruction. Thus when we do getDesc(add), we get the > descripiton corresponding to "ADD". When I was reading the code, I > got a feeling that if we are able to modify this selection of "ADD" > to "ADDS"( provided we somehow determine that we need ADDS here), > then everything else related to ARM instruction generation...

Hi Xiantao, I general I think the code in this patch is fine. I have a couple of nit-picking comments: > + if (target_mask&0x1) { The formatting here isn't quite what most of the kernel does. It would be better if you added spaces so it's a little easier to read, ie: if (target_mask & 0x1) { > + p = &__per_cpu_idtrs[cpu][0][0]; > + for (i = IA64_TR_ALLOC_BASE;

Hi Xiantao, I general I think the code in this patch is fine. I have a couple of nit-picking comments: > + if (target_mask&0x1) { The formatting here isn't quite what most of the kernel does. It would be better if you added spaces so it's a little easier to read, ie: if (target_mask & 0x1) { > + p = &__per_cpu_idtrs[cpu][0][0]; > + for (i = IA64_TR_ALLOC_BASE;

On Jul 14, 2008, at 12:59 PM, kapil anand wrote: > Hi all, > > I am using LLVM compiler and CodeGen for generating ARM binaries. > > I was going through the code for ARM backend. I noticed that the ARM > Condition field( Bits 31-28) is generated by converting the > conditions used in icmp and branch. For example, if I have following > C Code > > int a,b,c,d;

Hi all, I am using LLVM compiler and CodeGen for generating ARM binaries. I was going through the code for ARM backend. I noticed that the ARM Condition field( Bits 31-28) is generated by converting the conditions used in icmp and branch. For example, if I have following C Code int a,b,c,d; c = a+b; if(c==0) d = a + 10; Then I get ( Assembly Instructions with opcodes only) add *cmp*

...cture, > ARMInstrInfo.td file has complete description of the instructions which > modify the status flags. For example, we have description for both ADD and > ADDS. But the problem is that in LLVM, we have a single "ADD" Instruction. > Thus when we do getDesc(add), we get the descripiton corresponding to "ADD". > When I was reading the code, I got a feeling that if we are able to modify > this selection of "ADD" to "ADDS"( provided we somehow determine that we > need ADDS here), then everything else related to ARM instruction generation > h...