search for: depth0

...ormalized coordinates. */ const unsigned l = info->src.level; @@ -1151,14 +1157,12 @@ nv50_blit_3d(struct nv50_context *nv50, const struct pipe_blit_info *info) x1 /= fh; y0 /= fv; y1 /= fv; + if (nv50_miptree(src)->layout_3d) { + z /= u_minify(src->depth0, l); + dz /= u_minify(src->depth0, l); + } } - /* XXX: multiply by 6 for cube arrays ? */ - dz = (float)info->src.box.depth / (float)info->dst.box.depth; - z = (float)info->src.box.z; - if (nv50_miptree(src)->layout_3d) - z += 0.5f * dz; - BEGIN_NV...

..._tex.c @@ -115,12 +115,12 @@ nv50_create_texture_view(struct pipe_context *pipe, addr = mt->base.address; - if (mt->base.base.target == PIPE_TEXTURE_1D_ARRAY || - mt->base.base.target == PIPE_TEXTURE_2D_ARRAY) { + depth = MAX2(mt->base.base.array_size, mt->base.base.depth0); + + if (mt->base.base.array_size > 1) { + /* there doesn't seem to be a base layer field in TIC */ addr += view->pipe.u.tex.first_layer * mt->layer_stride; depth = view->pipe.u.tex.last_layer - view->pipe.u.tex.first_layer + 1; - } else { - depth...

...= 0; + static int no_swizzle = -1; + if(no_swizzle < 0) + no_swizzle = debug_get_bool_option("NOUVEAU_NO_SWIZZLE", FALSE); + + /* Non-uniform pitch textures must be POT */ + if (pt->width0 & (pt->width0 - 1) || + pt->height0 & (pt->height0 - 1) || + pt->depth0 & (pt->depth0 - 1) + ) + uniform_pitch = 1; + + /* All texture formats except compressed ones can be swizzled + * Unsure about depth, let's prevent swizzling for now + */ + if (pt->tex_usage & (PIPE_TEXTURE_USAGE_PRIMARY | + PIPE_TEXTURE_USAGE_DISPLAY_T...

...= 0; + static int no_swizzle = -1; + if(no_swizzle < 0) + no_swizzle = debug_get_bool_option("NOUVEAU_NO_SWIZZLE", FALSE); + + /* Non-uniform pitch textures must be POT */ + if (pt->width0 & (pt->width0 - 1) || + pt->height0 & (pt->height0 - 1) || + pt->depth0 & (pt->depth0 - 1) + ) + uniform_pitch = 1; + + /* All texture formats except compressed ones can be swizzled + * Unsure about depth, let's prevent swizzling for now + */ + if (pt->tex_usage & (PIPE_TEXTURE_USAGE_PRIMARY | + PIPE_TEXTURE_USAGE_DISPLAY_T...

On Thu, Sep 3, 2015 at 7:25 AM, Hans de Goede <hdegoede at redhat.com> wrote: > On nv3x we will likely end up using the cpu to do color resolving for msaa > blits. Disable msaa on these cards so that we do not end up using the cpu. Actually the CPU fallback won't do scaled, so it's stuck with SIFM or assert(false). Which isn't great, but... it's what the HW does. I

This patch series silences some unknown cap warnings and fixes up coding style (patch 1+4). The most important part of this series are the two patches in the middle. They rework the state_fb code, so that we are able to render to not 64 byte aligned targets, as this is the only real use-case for render temporaries this allows us to drop temp code completely and simplifies a lot

...tic[2] = GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR; > + tic[3] |= > + ((mt->level[0].tile_mode & 0x0f0) >> 4 << 3) | > + ((mt->level[0].tile_mode & 0xf00) >> 8 << 6); > + > + depth = MAX2(mt->base.base.array_size, mt->base.base.depth0); > + > + if (mt->base.base.array_size > 1) { > + /* there doesn't seem to be a base layer field in TIC */ > + address += view->pipe.u.tex.first_layer * mt->layer_stride; > + depth = view->pipe.u.tex.last_layer - view->pipe.u.tex.first_layer + 1...

Hi All, Here is a bunch of fixes for nv30 cards, the first patch is a resend of a patch I send a while back. AFAICT that one is ready for merging, but it is not entirely clear to me what the process is for getting (nouveau) mesa patches merged. Should I request commit rights, and push my own patches once they have been reviewed ? Regards, Hans

...ew->pipe; + } + + tic[2] = GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR; + tic[3] |= + ((mt->level[0].tile_mode & 0x0f0) >> 4 << 3) | + ((mt->level[0].tile_mode & 0xf00) >> 8 << 6); + + depth = MAX2(mt->base.base.array_size, mt->base.base.depth0); + + if (mt->base.base.array_size > 1) { + /* there doesn't seem to be a base layer field in TIC */ + address += view->pipe.u.tex.first_layer * mt->layer_stride; + depth = view->pipe.u.tex.last_layer - view->pipe.u.tex.first_layer + 1; + } + tic[1] = add...

..._2_HEADER_VERSION_BLOCKLINEAR; >> + tic[3] |= >> + ((mt->level[0].tile_mode & 0x0f0) >> 4 << 3) | >> + ((mt->level[0].tile_mode & 0xf00) >> 8 << 6); >> + >> + depth = MAX2(mt->base.base.array_size, mt->base.base.depth0); >> + >> + if (mt->base.base.array_size > 1) { >> + /* there doesn't seem to be a base layer field in TIC */ >> + address += view->pipe.u.tex.first_layer * mt->layer_stride; >> + depth = view->pipe.u.tex.last_layer - view->pipe.u...

...n that wants to use a depth buffer always crashes, including glxgears: glxgears: dri2.c:906: dri2_allocate_textures: Assertion `*zsbuf' failed. I debugged the assertion with gdb: templ structure contents passed to resource_create(): $2 = {reference = {count = 0}, width0 = 300, height0 = 300, depth0 = 1, array_size = 1, format = PIPE_FORMAT_Z24X8_UNORM, target = PIPE_TEXTURE_2D, last_level = 0, nr_samples = 0, nr_storage_samples = 0, usage = 0, bind = 1, flags = 0, next = 0x0, screen = 0x0} In nv50_miptree_create() in gallium/drivers/nouveau/nv50/nv50_miptree.c:389 the call to nouveau_bo_...

...nv84_video_buffer_surfaces; > + buffer->base.interlaced = true; By storing the number of planes, will be able to demagic some constants later on buffer->num_planes = 2; > + > + memset(&templ, 0, sizeof(templ)); > + templ.target = PIPE_TEXTURE_2D_ARRAY; > + templ.depth0 = 1; > + templ.bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET; > + templ.format = PIPE_FORMAT_R8_UNORM; > + templ.width0 = align(template->width, 2); > + templ.height0 = align(template->height, 4) / 2; > + templ.flags = NV50_RESOURCE_FLAG_VIDEO; > + temp...

..._is_compressed(pt->format)); + + mt->layout_3d = pt->target == PIPE_TEXTURE_3D; + + mt->level[0].tile_mode = 0x20; + mt->level[0].pitch = align(pt->width0 * blocksize, 64); + mt->total_size = align(pt->height0, 16) * mt->level[0].pitch * (mt->layout_3d ? pt->depth0 : 1); + + if (pt->array_size > 1) { + mt->layer_stride = align(mt->total_size, NV50_TILE_SIZE(0x20)); + mt->total_size = mt->layer_stride * pt->array_size; + } +} + +static void nv50_miptree_init_layout_tiled(struct nv50_miptree *mt) { struct pipe_resource *...

...buffer->num_planes = 2; nvc0_video does that. I find that incredibly confusing. It's always 2, and they are of diff size. I prefer my bike-shed color :) > >> + >> + memset(&templ, 0, sizeof(templ)); >> + templ.target = PIPE_TEXTURE_2D_ARRAY; >> + templ.depth0 = 1; >> + templ.bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET; >> + templ.format = PIPE_FORMAT_R8_UNORM; >> + templ.width0 = align(template->width, 2); >> + templ.height0 = align(template->height, 4) / 2; >> + templ.flags = NV50_RESOURCE_FLAG_...

..._is_compressed(pt->format)); + + mt->layout_3d = pt->target == PIPE_TEXTURE_3D; + + mt->level[0].tile_mode = 0x20; + mt->level[0].pitch = align(pt->width0 * blocksize, 64); + mt->total_size = align(pt->height0, 16) * mt->level[0].pitch * (mt->layout_3d ? pt->depth0 : 1); + + if (pt->array_size > 1) { + mt->layer_stride = align(mt->total_size, NV50_TILE_SIZE(0x20)); + mt->total_size = mt->layer_stride * pt->array_size; + } +} + +static void nv50_miptree_init_layout_tiled(struct nv50_miptree *mt) { struct pipe_resource *...

...vc0_video does that. I find that incredibly confusing. It's always 2, > and they are of diff size. I prefer my bike-shed color :) > >> >>> + >>> + memset(&templ, 0, sizeof(templ)); >>> + templ.target = PIPE_TEXTURE_2D_ARRAY; >>> + templ.depth0 = 1; >>> + templ.bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET; >>> + templ.format = PIPE_FORMAT_R8_UNORM; >>> + templ.width0 = align(template->width, 2); >>> + templ.height0 = align(template->height, 4) / 2; >>> + templ.flags =...

Hello, I have my work on the nv vpe video decoder in a functional state. In case you didn't know this decoder accelerates mpeg2 video at the idct/mc level. I have verified that it works on nv40 hardware. I believe it works on nv30 hardware (and maybe some earlier hardware), but I cannot verify since I have none. I will reply with patches against the kernel, drm, ddx and mesa for

Hi, On 03-08-15 20:09, Ilia Mirkin wrote: > On Mon, Aug 3, 2015 at 1:31 PM, Hans de Goede <hdegoede at redhat.com> wrote: >> Hi, >> >> >> On 03-08-15 17:36, Ilia Mirkin wrote: >>> >>> On Mon, Aug 3, 2015 at 9:02 AM, Hans de Goede <hdegoede at redhat.com> wrote: >>>> >>>> Hi, >>>> >>>> On

As it turns out, with the proprietary firmware, the VP3 and VP4 interfaces are identical. Furthermore, this is all already implemented for nvc0. So these patches (a) move the easily sharable bits of the nvc0 implementation into the nouveau directory, and then (b) implement the other parts in nv50. The non-shared parts are still largely copies, but there are some differences, not the least of which

From: Ben Skeggs <bskeggs at redhat.com> Signed-off-by: Ben Skeggs <bskeggs at redhat.com> --- src/gallium/drivers/nouveau/nv50/g80_defs.xml.h | 279 ++++++++++++++++++++++++ 1 file changed, 279 insertions(+) create mode 100644 src/gallium/drivers/nouveau/nv50/g80_defs.xml.h diff --git a/src/gallium/drivers/nouveau/nv50/g80_defs.xml.h