Displaying 5 results from an estimated 5 matches for "den0024a".
2016 Jan 14
4
RFC: non-temporal fencing in LLVM IR
...M, Tim Northover <t.p.northover at gmail.com>
wrote:
> > I haven't touched ARMv8 in a few years so I'm rusty on the non-temporal
> > details for that ISA. I lifted this example from here:
> >
> >
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/CJACGJJF.html
> >
> > Which is correct?
>
> FWIW, I agree with John here. The example I'd give for the unexpected
> behaviour allowed in the spec is:
>
> .Lwait_for_data:
> ldr x0, [x3]
> cbz x0, .Lwait_for_data
> ldnp x2, x1, [x0]
>
> where...
2016 Jan 14
2
RFC: non-temporal fencing in LLVM IR
...gt; wrote:
>>
>>> > I haven't touched ARMv8 in a few years so I'm rusty on the non-temporal
>>> > details for that ISA. I lifted this example from here:
>>> >
>>> >
>>> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/CJACGJJF.html
>>> >
>>> > Which is correct?
>>>
>>> FWIW, I agree with John here. The example I'd give for the unexpected
>>> behaviour allowed in the spec is:
>>>
>>> .Lwait_for_data:
>>> ldr x0, [x3]
>>>...
2016 Jan 13
2
RFC: non-temporal fencing in LLVM IR
...>
> order, but the CPU executing the instructions will observe them in program
> order.
>
I haven't touched ARMv8 in a few years so I'm rusty on the non-temporal
details for that ISA. I lifted this example from here:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/CJACGJJF.html
Which is correct?
I have no idea if that affects anything in this RFC though.
>
Agreed, but I don't want to be misleading! The current example serves as a
good justification for non-temporal read barriers, it would be a shame to
justify myself on incorrect data :-)
Joh...
2016 Jan 14
2
RFC: non-temporal fencing in LLVM IR
...ouched ARMv8 in a few years so I'm rusty on the
>>>>> non-temporal
>>>>> > details for that ISA. I lifted this example from here:
>>>>> >
>>>>> >
>>>>> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/CJACGJJF.html
>>>>> >
>>>>> > Which is correct?
>>>>>
>>>>> FWIW, I agree with John here. The example I'd give for the unexpected
>>>>> behaviour allowed in the spec is:
>>>>>
>>>>> .L...
2016 Jan 13
4
RFC: non-temporal fencing in LLVM IR
Hello, fencing enthusiasts!
*TL;DR:* We'd like to propose an addition to the LLVM memory model
requiring non-temporal accesses be surrounded by non-temporal load barriers
and non-temporal store barriers, and we'd like to add such orderings to the
fence IR opcode.
We are open to different approaches, hence this email instead of a patch.
*Who's "we"?*
Philip Reames brought