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...y. The AVX2 spec includes gather; whether it's slow or fast is an implementation detail. We need a feature bit / cost model entry somewhere to signify this, so we're not overloading the meaning of the architectural features with that implementation detail. On Fri, Feb 26, 2016 at 12:23 PM, Demikhovsky, Elena < elena.demikhovsky at intel.com> wrote: > No. Gather operation is slow on AVX2 processors. > > > > - * Elena* > > > > *From:* zhi chen [mailto:zchenhn at gmail.com] > *Sent:* Thursday, February 25, 2016 20:48 > *To:* Sanjay Patel <spatel a...

...s gather; > whether it's slow or fast is an implementation detail. We need a feature > bit / cost model entry somewhere to signify this, so we're not overloading > the meaning of the architectural features with that implementation detail. > > On Fri, Feb 26, 2016 at 12:23 PM, Demikhovsky, Elena < > elena.demikhovsky at intel.com> wrote: > >> No. Gather operation is slow on AVX2 processors. >> >> >> >> - * Elena* >> >> >> >> *From:* zhi chen [mailto:zchenhn at gmail.com] >> *Sent:* Thursday, February 25...

...8:28 AM, Sanjay Patel <spatel at rotateright.com> wrote: > I don't think gather has been enabled for AVX2 as of r261875. > Masked load/store were enabled for AVX with: > http://reviews.llvm.org/D16528 / http://reviews.llvm.org/rL258675 > > On Wed, Feb 24, 2016 at 11:39 PM, Demikhovsky, Elena < > elena.demikhovsky at intel.com> wrote: > >> Yes, masked load/store/gather/scatter are completed. >> >> >> >> - * Elena* >> >> >> >> *From:* zhi chen [mailto:zchenhn at gmail.com] >> *Sent:* Thursday, Februar...

No. Gather operation is slow on AVX2 processors. - Elena From: zhi chen [mailto:zchenhn at gmail.com] Sent: Thursday, February 25, 2016 20:48 To: Sanjay Patel <spatel at rotateright.com> Cc: Demikhovsky, Elena <elena.demikhovsky at intel.com>; Nema, Ashutosh <Ashutosh.Nema at amd.com>; llvm-dev <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] how to force llvm generate gather intrinsic It seems that http://reviews.llvm.org/D15690 only implemented gather/scatter for AVX-512,...

Yes, masked load/store/gather/scatter are completed. - Elena From: zhi chen [mailto:zchenhn at gmail.com] Sent: Thursday, February 25, 2016 01:20 To: Demikhovsky, Elena <elena.demikhovsky at intel.com> Cc: Sanjay Patel <spatel at rotateright.com>; Nema, Ashutosh <Ashutosh.Nema at amd.com>; llvm-dev <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] how to force llvm generate gather intrinsic Hi Elena, Are the masked_load and gath...

...tion like %a = loadm <4 x i32>* %addr, <4 x i32> %passthru, i32 4, <4 x i1>%mask is possible, but may be not very useful for most of targets. So we start from intrinsics. - Elena From: Owen Anderson [mailto:resistor at mac.com] Sent: Monday, October 27, 2014 18:59 To: Demikhovsky, Elena Cc: llvmdev at cs.uiuc.edu; dag at cray.com Subject: Re: [LLVMdev] Adding masked vector load and store intrinsics Since this is something that you expect to be supported on all targets, and which requires extensive type overloading, it seems like a perfect candidate for being an Instruction...

we just follow a common recommendation to start with intrinsics: http://llvm.org/docs/ExtendingLLVM.html - Elena From: Owen Anderson [mailto:resistor at mac.com] Sent: Sunday, October 26, 2014 23:57 To: Demikhovsky, Elena Cc: llvmdev at cs.uiuc.edu; dag at cray.com Subject: Re: [LLVMdev] Adding masked vector load and store intrinsics What is the motivation for using intrinsics versus adding new instructions? —Owen On Oct 24, 2014, at 4:24 AM, Demikhovsky, Elena <elena.demikhovsky at intel.com<mailto:...

I don't think gather has been enabled for AVX2 as of r261875. Masked load/store were enabled for AVX with: http://reviews.llvm.org/D16528 / http://reviews.llvm.org/rL258675 On Wed, Feb 24, 2016 at 11:39 PM, Demikhovsky, Elena < elena.demikhovsky at intel.com> wrote: > Yes, masked load/store/gather/scatter are completed. > > > > - * Elena* > > > > *From:* zhi chen [mailto:zchenhn at gmail.com] > *Sent:* Thursday, February 25, 2016 01:20 > *To:* Demikhovsky, Elena &l...

...the cost mentioned for same operation in SSE2ConversionTbl. Below patch from Cong Hou reduce cost for same operation in SSE2 mode. http://reviews.llvm.org/rL256194 Looks like as the part of same patch we should reduce cost for TRUNCATE v16i32 to v16i8 in SSE4.1 as well. Regards, Ashutosh From: Demikhovsky, Elena [mailto:elena.demikhovsky at intel.com] Sent: Monday, April 11, 2016 9:05 PM To: Nema, Ashutosh <Ashutosh.Nema at amd.com> Cc: llvm-dev <llvm-dev at lists.llvm.org>; Zuckerman, Michael <michael.zuckerman at intel.com> Subject: RE: X86 TRUNCATE cost for AVX & AVX2 mode...

----- Original Message ----- > From: "Elena Demikhovsky" <elena.demikhovsky at intel.com> > To: "Hal J. Finkel" <hfinkel at anl.gov>, "Eli Friedman" > <eli.friedman at gmail.com> > Cc: "llvm-dev" <llvm-dev at lists.llvm.org>, "Richard Smith" > <richard-llvm at metafoo.co...

...in the near future. >> >> What do others think? >> >> Philip >> >> >> -------- Forwarded Message -------- >> Subject: [PATCH] D17497: Support arbitrary address space for intrinsics >> Date: Mon, 22 Feb 2016 08:39:38 +0000 >> From: Elena Demikhovsky <elena.demikhovsky at intel.com> >> Reply-To: reviews+D17497+public+90f3d1b9468ba8ca at reviews.llvm.org >> To: elena.demikhovsky at intel.com, apilipenko at azulsystems.com, >> listmail at philipreames.com, ayal.zaks at intel.com, >> Matthew.Arsenault at amd.com,...

...StackPtr, MachinePointerInfo(), EltVT); > } I assume that we need the opposite - if (.. < 8) getExtLoad // VT should be MVT::i8, MemVT should be MVT::i1 else getLoad - Elena From: jingu at codeplay.com [mailto:jingu at codeplay.com] Sent: Monday, September 18, 2017 13:40 To: Demikhovsky, Elena <elena.demikhovsky at intel.com>; daniel_l_sanders at apple.com <daniel_l_sanders at apple.com>; Jon Chesterfield <jonathanchesterfield at gmail.com> Cc: llvm-dev at lists.llvm.org Subject: Re: Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT' um......

...ch splat element) redundant instructions (broadcast is insert+shuffle), hoist them outside the loop on some stage. Then look for them on CodeGenPreare pass, sink them back and rebuild the CFG. - Elena From: Nadav Rotem [mailto:nrotem at apple.com] Sent: Monday, March 02, 2015 19:01 To: Demikhovsky, Elena Cc: llvmdev at cs.uiuc.edu; Duncan P. N. Exon Smith; dag at cray.com; Philip Reames (listmail at philipreames.com); Hal Finkel (hfinkel at anl.gov); Chandler Carruth (chandlerc at gmail.com) Subject: Re: Extending Vector GEP - proposal I don’t have a strong opinion on this. The current GEP...

AFAIK, there is no additional penalty for AMD processors. From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Chandler Carruth Sent: Monday, December 15, 2014 3:57 AM To: Demikhovsky, Elena Cc: llvmdev at cs.uiuc.edu Subject: Re: [LLVMdev] Memory alignment model on AVX, AVX2 and AVX-512 targets FWIW, this makes sense to me. I'd be interested to hear from folks that are supporting AMD processors which do support AVX to ensure that there isn't an undue runtime penalty fo...

Please open a bugzilla ticket and attach your testcase. It will allow us to debug and fix the problem. Thanks - Elena From: JinGu [mailto:jingu at codeplay.com] Sent: Saturday, September 16, 2017 00:38 To: Demikhovsky, Elena <elena.demikhovsky at intel.com>; daniel_l_sanders at apple.com <daniel_l_sanders at apple.com>; Jon Chesterfield <jonathanchesterfield at gmail.com> Cc: llvm-dev at lists.llvm.org Subject: Re: Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT' Hi El...

Hi Elena, Are the masked_load and gather working now? Best, Zhi On Sat, Jan 23, 2016 at 12:06 PM, Demikhovsky, Elena < elena.demikhovsky at intel.com> wrote: > Ø Can we legalize the same set of masked load/store operations for AVX1 > as AVX2? > > Yes, of course. > > > > - * Elena* > > > > *From:* Sanjay Patel [mailto:spatel at rotateright.com] > *Sent...

...teger primary induction variable (compile-generated) for loop control. So, (future) FORTRAN usage doesn’t seem to be a good example for promoting support for case A (= FP primary induction variable). From: Chandler Carruth [mailto:chandlerc at google.com] Sent: Thursday, May 19, 2016 7:03 PM To: Demikhovsky, Elena <elena.demikhovsky at intel.com>; anemet at apple.com; Sanjoy Das <sanjoy at playingwithpointers.com> Cc: Saito, Hideki <hideki.saito at intel.com>; llvm-dev <llvm-dev at lists.llvm.org>; Andrew Trick <atrick at apple.com> Subject: Re: [llvm-dev] Working on FP S...

Hi Renato, I fully agree with you, but indexed load and store is the next step. I'm asking to review gather and scatter code. Thanks. - Elena -----Original Message----- From: Renato Golin [mailto:renato.golin at linaro.org] Sent: Thursday, April 16, 2015 17:17 To: Demikhovsky, Elena Cc: llvmdev at cs.uiuc.edu; Chandler Carruth; James Molloy Subject: Re: [LLVMdev] Code review for gather and scatter intrinsics On 16 April 2015 at 14:44, Demikhovsky, Elena <elena.demikhovsky at intel.com> wrote: > http://reviews.llvm.org/D7665. > I presented this work on LLVM...

> On Oct 26, 2014, at 8:22 AM, Hal Finkel <hfinkel at anl.gov> wrote: > > ----- Original Message ----- >> From: "Elena Demikhovsky" <elena.demikhovsky at intel.com> >> To: "Hal Finkel" <hfinkel at anl.gov> >> Cc: llvmdev at cs.uiuc.edu >> Sent: Sunday, October 26, 2014 10:17:49 AM >> Subject: RE: [LLVMdev] Masked vector intrinsics and name mangling >> >> Hal, than...

...loop control. So, (future) FORTRAN usage doesn’t seem to be > a good example for promoting support for case A (= FP primary induction variable). > > >   <> > <>From: Chandler Carruth [mailto:chandlerc at google.com] > Sent: Thursday, May 19, 2016 7:03 PM > To: Demikhovsky, Elena <elena.demikhovsky at intel.com>; anemet at apple.com; Sanjoy Das <sanjoy at playingwithpointers.com> > Cc: Saito, Hideki <hideki.saito at intel.com>; llvm-dev <llvm-dev at lists.llvm.org>; Andrew Trick <atrick at apple.com> > Subject: Re: [llvm-dev] Worki...