Displaying 6 results from an estimated 6 matches for "demarshalling".
2008 May 08
2
Testing render :text without has_text
A controller I''m trying to test simply delivers a text string to the
client, which then demarshalls it to retrieve some objects. I want to
test that the returned string is correct.
I don''t want to compare the string character-by-character with
response.has_text because that ties me to the implementation of the
Marshall class. Instead, I just want to demarshall the string
2012 May 25
0
[LLVMdev] generating LLVM code that meets the C ABI
...e platforms but x86_64 would be OK
for now).
I know that LLVM doesn't handle this completely automatically (e.g.
the type {i32,i32} should be passed as a single i64 on x86_64 linux).
Is there any library that automates the generation of function
declarations meeting the ABI and emit marshalling/demarshalling code
from LLVM's types?
I would imagine that Clang needs to do this internally, where does
this code live?
Thanks for your help!
Zach
2007 Jun 12
0
[PATCH][libxenapi] Fix segmentaion fault in libxenapi
When calling xen_vbd_set_mode(), libxenapi attempted to convert the enum
mode parameter to a string twice - resulting in segfault. Removed first
conversion since conversion is taking place in marshalling/demarshalling
layer. Fixed similar double enum conversion in other places as well.
Regards,
Jim
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2006 Mar 23
15
Is Rails Appropriate for our Project?
I realize this subject is redundant for this community, but I''m hoping
the Rails community can provide me with some additional ammunition to
help push a rails project I''m pitching over the proverbial tipping point
at my company.
The Situation:
I''m the lead architect at a large bay area retailer. My team and I are
currently suffering through the process of paying
2016 Mar 28
0
RFC: atomic operations on SI+
...b/Target/AMDGPU/SIISelLowering.cpp
> @@ -263,6 +263,12 @@ SITargetLowering::SITargetLowering(TargetMachine &TM,
> setOperationAction(ISD::FDIV, MVT::f32, Custom);
> setOperationAction(ISD::FDIV, MVT::f64, Custom);
>
> + // GCN CMP_SWAP needs input marshalling, and output demarshalling
> + setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
> + // We can't return success/failure, only the old value,
> + // let LLVM add the comparison
> + setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i32, Expand);
> +
> setTargetDAGCombine(ISD::FAD...
2016 Mar 25
2
RFC: atomic operations on SI+
Hi Tom, Matt,
I'm working on a project that needs few coherent atomic operations (HSA
mode: load, store, compare-and-swap) for std::atomic_uint in HCC.
the attached patch implements atomic compare and swap for SI+
(untested). I tried to stay within what was available, but there are
few issues that I was unsure how to address:
1.) it currently uses v2i32 for both input and output. This