search for: demandedbits

...bits - IR shifts don't mask their shift amounts. I.e we can't replace `x >> (32-y)` with `x >> (-y)`, which would be legal transform should we not demand those bits. We very much demand them. We just know those bits to be zero. And i'm not sure how to convey that to SimplifyDemandedBits(). I can't pass the Known down the stack, the function resets it first thing, so Known can only be passed from callee to the caller. This is why i'm asking whether anyone is concerned if we proceed with https://reviews.llvm.org/D68150 On Tue, Oct 1, 2019 at 10:44 PM Nikita Popov <nikit...

On Mon, Oct 7, 2019 at 11:32 AM Roman Lebedev <lebedev.ri at gmail.com> wrote: > > Bump. Any further thoughts here? > > To recap - i don't really see how this can be a demandedbits problem - we do > demand all those bits, we just know they must be zero. > (i would love to be proven wrong though!) > > Roman. > > On Tue, Oct 1, 2019 at 11:17 PM Roman Lebedev <lebedev.ri at gmail.com> wrote: > > > > The thing is, we *don't* "not deman...

...so everything else that may have to deal with looking past extension of shift amount doesn't need to be modified. > 2) Having a general multiple use demanded use routine would be very > powerful. Is it worth exploring the harder topic for generality? There is some support for multi-use demandedbits in backend. As for middle-end i'm not sure. For sure, having that powerful mechanism may be useful, in general. > 3) If we had an anyextend IR node, it might be reasonable to eagerly > produce the duplicate nodes, and rely on later CSE. I keep running > across cases where we have an...

A rotate intrinsic should be relatively close in cost/complexity to the existing bswap. A grep of intrinsic::bswap says we'd probably add code in: InstCombine InstructionSimplify ConstantFolding DemandedBits ValueTracking VectorUtils SelectionDAGBuilder But I don't think it's fair to view those additions as pure added cost. As an example, consider that we have to add hacks to EarlyCSE to recognize multi-IR-instruction min/max/abs patterns. Intrinsics just work as-is there. So if you search for...

...good. John On 05/17/2018 11:14 AM, Sanjay Patel wrote: > A rotate intrinsic should be relatively close in cost/complexity to the > existing bswap. > > A grep of intrinsic::bswap says we'd probably add code in: > InstCombine > InstructionSimplify > ConstantFolding > DemandedBits > ValueTracking > VectorUtils > SelectionDAGBuilder > > But I don't think it's fair to view those additions as pure added cost. > As an example, consider that we have to add hacks to EarlyCSE to > recognize multi-IR-instruction min/max/abs patterns. Intrinsics just...

On 5/16/18 1:58 PM, Sanjay Patel via llvm-dev wrote: > An informal metric might be: if the operation is supported as a > primitive op or built-in in source languages and it is supported as a > single target instruction, can we guarantee that 1-to-1 translation > through optimization? It seems perfectly reasonable for LLVM users to expect this to happen reliably. I'd like to

...> > A rotate intrinsic should be relatively close in > cost/complexity to the existing bswap. > > A grep of intrinsic::bswap says we'd probably add code in: > InstCombine > InstructionSimplify > ConstantFolding > DemandedBits > ValueTracking > VectorUtils > SelectionDAGBuilder > > But I don't think it's fair to view those additions as pure > added cost. As an example, consider that we have to add hacks > to EarlyCSE to recognize multi-IR-instru...

Hello All, I am trying to understand the demanded-bits pass. The example in the source code (below) seems quite explicit. In the example, only 16 bits from a 32 bit variable in IR are demanded and therefore the variable is truncated to a 16 bit variable. %1 = add i32 %x, %y %2 = trunc i32 %1 to i16 However I was wondering if for example, the addition demanded, say 18 bits, would this pass

In https://reviews.llvm.org/D68103 the InstCombine learned that shift-by-sext is simply a shift-by-zext. But the transform is limited to single-use sext. We can quite trivially get a case where there are two shifts by the same sext: https://godbolt.org/z/j6mO3t <- We should handle those cases. In https://reviews.llvm.org/D68103#1686130 Sanjay Patel notes that this sext is intrusive for

...reeAnalysis: Stores no pointers to other analyses. > > > > > > > > > > > > > > > PostDominatorTreeAnalysis: Stores no pointers to other > > > > > analyses. > > > > > > > > > > > > > > > DemandedBitsAnalysis: Stores pointers to AssumptionCache and > > > > > DominatorTree > > > > > > > > > > > > > > > DominanceFrontierAnalysis: Stores no pointers to other > > > > > analyses. > > > > > (uses DominatorTr...

...> > > > > > > > > > PostDominatorTreeAnalysis: Stores no pointers to other > > > > > > > analyses. > > > > > > > > > > > > > > > > > > > > > > > > > > > > DemandedBitsAnalysis: Stores pointers to AssumptionCache > > > > > > > and > > > > > > > DominatorTree > > > > > > > > > > > > > > > > > > > > > > > > > > > > DominanceFrontierAna...

...> > > > > > > > > > PostDominatorTreeAnalysis: Stores no pointers to other > > > > > > > analyses. > > > > > > > > > > > > > > > > > > > > > > > > > > > > DemandedBitsAnalysis: Stores pointers to AssumptionCache > > > > > > > and > > > > > > > DominatorTree > > > > > > > > > > > > > > > > > > > > > > > > > > > > DominanceFrontierAna...

...ters to other analyses. >>>>>> (uses LoopInfo to "recalculate" though) >>>>>> DominatorTreeAnalysis: Stores no pointers to other analyses. >>>>>> PostDominatorTreeAnalysis: Stores no pointers to other analyses. >>>>>> DemandedBitsAnalysis: Stores pointers to AssumptionCache >>>>>> and DominatorTree >>>>>> DominanceFrontierAnalysis: Stores no pointers to other analyses. >>>>>> (uses DominatorTreeAnalysis for "recalculate" though). >>>>>> LoopInf...

...alyses. >>>>>>> (uses LoopInfo to "recalculate" though) >>>>>>> DominatorTreeAnalysis: Stores no pointers to other analyses. >>>>>>> PostDominatorTreeAnalysis: Stores no pointers to other analyses. >>>>>>> DemandedBitsAnalysis: Stores pointers to AssumptionCache >>>>>>> and DominatorTree >>>>>>> DominanceFrontierAnalysis: Stores no pointers to other analyses. >>>>>>> (uses DominatorTreeAnalysis for "recalculate" though). >>>>>...

...t;> BranchProbabilityAnalysis: Stores no pointers to other analyses. (uses >>> LoopInfo to "recalculate" though) >>> DominatorTreeAnalysis: Stores no pointers to other analyses. >>> PostDominatorTreeAnalysis: Stores no pointers to other analyses. >>> DemandedBitsAnalysis: Stores pointers to AssumptionCache >>> and DominatorTree >>> DominanceFrontierAnalysis: Stores no pointers to other analyses. >>> (uses DominatorTreeAnalysis for "recalculate" though). >>> LoopInfo: Uses DominatorTreeAnalysis for "recalcul...

<div> </div><div><div><p>Carry-less multiplication[1] instructions exist (at least optionally) on many architectures: armv8, RISC-V, x86_64, POWER, SPARC, C64x, and possibly more.</p><p>This proposal is to add a <code>llvm.clmul</code> instruction. Or if that is contentious, <code>llvm.experimental.bitmanip.clmul</code> instruction.