search for: delaycycl

...rved" flag is not ideal, but it is > sort-of a consequence of the above mentioned two limitations (plus the way > how the Haswell and Broadwell models were originally designed). > > I hope it helps, > -Andrea > > > Food for thought... > > It would be easy to add a DelayCycles vector to SchedWriteRes to indicate > the relative start cycle for each reserved resource. That would effectively > model dependent uOps. > > NumMicroOps is only meant to model any general limitation of the cpu > frontend to issue/rename/retire micro-ops. So, yes, there's no wa...

...on, the presence of a "reserved" flag is not ideal, but it is sort-of a consequence of the above mentioned two limitations (plus the way how the Haswell and Broadwell models were originally designed). > > I hope it helps, > -Andrea Food for thought... It would be easy to add a DelayCycles vector to SchedWriteRes to indicate the relative start cycle for each reserved resource. That would effectively model dependent uOps. NumMicroOps is only meant to model any general limitation of the cpu frontend to issue/rename/retire micro-ops. So, yes, there's no way to associate resources...

Hi Andrew, I seem to be making good progress on the P5600 scheduler using the new machine model but I've got a few questions about it. How would you represent an instruction that splits into two micro-ops and is dispatched to two different reservation stations? For example, I have two reservation stations (AGQ and FPQ). An FPU load instruction is split into a load micro-op which is

Hi, I’m trying to work out the behavior of llvm-mca on instructions with ProcResGroups. My current understanding is: When an instruction requests a port group (e.g., HWPort015) and all of its atomic sub-resources (e.g., HWPort0,HWPort1,HWPort5), HWPort015 is marked as “reserved” and is issued in parallel with HWPort0, HWPort1, and HWPort5, blocking future instructions from reserving HWPort015

...ossible to handle special cases requiring the itinerary's precision without using an itinerary by either pluging custom logic into the MachineSchedStrategy, or extending the new machine model... [2] To model in-order pipeline resource we could - add a field to MCWriteProcResEntry + unsigned DelayCycles; - Modify the table gen code in SubtargetEmitter to record the delay. We already to this: // If this resource is already used in this sequence, add the current // entry's cycles so that the same resource appears to be used // serially, rather than multiple parallel us...