search for: delalama

2009/9/15 Carlos Sánchez de La Lama <carlos.delalama at urjc.es>: > Hi all, > > I am creating a function and trying to call it using the LLVM API. It > seems that whenever the function type includes an opaque-typed > parameter, the CallInst::Create call causes an assert: > > Assertion failed: ((i >= FTy->getNumParams() |...

Hi all, I am creating a function and trying to call it using the LLVM API. It seems that whenever the function type includes an opaque-typed parameter, the CallInst::Create call causes an assert: Assertion failed: ((i >= FTy->getNumParams() || FTy->getParamType(i) == Params[i]->getType()) && "Calling a function with a bad signature!"), function init, file

...d then it would become a real (and burning) issue. This might be our chance to outperform GCC RISC centric philosophy in an elegant and powerful way. First step to healing is to recognize that we have an issue ;) Sergei -----Original Message----- From: Carlos Sánchez de La Lama [mailto:carlos.delalama at urjc.es] Sent: Tuesday, October 25, 2011 4:24 AM To: Sergei Larin Cc: 'Evan Cheng'; 'Stripf, Timo'; 'LLVM Dev' Subject: RE: [LLVMdev] VLIW Ports Hi Sergei, > What would you say to a some sort of a "global cycle" field/marker to > determine all instruc...

Hi all, >>> I would favor calling conventions over metadata for the simple >>> reason that this maps more cleanly to the device model. Device and >>> kernel functions are represented differently in PTX, including >>> (sometimes) the way parameters are passed. >> For the record, marking the kernels with "calling conventions" >> instead

...nd burning) issue. This might be our chance to outperform GCC RISC centric philosophy in an elegant and powerful way. > > First step to healing is to recognize that we have an issue ;) > > Sergei > > -----Original Message----- > From: Carlos Sánchez de La Lama [mailto:carlos.delalama at urjc.es] > Sent: Tuesday, October 25, 2011 4:24 AM > To: Sergei Larin > Cc: 'Evan Cheng'; 'Stripf, Timo'; 'LLVM Dev' > Subject: RE: [LLVMdev] VLIW Ports > > Hi Sergei, > >> What would you say to a some sort of a "global cycle" field...

Hi Sergei, > What would you say to a some sort of a "global cycle" field/marker to > determine all instructions scheduled at a certain "global" cycle. That way > the "bundle"/packet/multiop can be identified at any time via a common > "global cycle" value. But RA would need to know about this global cycle field, right? Cause a register can be

Hi Timo, your approach is quite similar to the one in the patch I sent a couple of weeks ago. I also have the Bundle (derivate from MachineInstruction so I call it "MachineInstructionBundle") and pack/unpack so RegAlloc works on the bundles… I really think this is the way to incorporate VLIW support to LLVM. I guess a need for some of this to make to LLVM trunk is to have a backend

Evan, Timo, Carlos (and everyone else), I have somewhat similar interest. What would you say to a some sort of a "global cycle" field/marker to determine all instructions scheduled at a certain "global" cycle. That way the "bundle"/packet/multiop can be identified at any time via a common "global cycle" value. I could see that being set first in pre-ra

..."Uses remain when a value is destroyed!"' failed. > 0 opt 0x0848e569 > Stack dump: > > > What suggestions do you have for solve this problem? ------------------------------ Message: 8 Date: Thu, 06 Oct 2011 14:14:07 +0300 From: Carlos S?nchez de La Lama <carlos.delalama at urjc.es> Subject: Re: [LLVMdev] VLIW Ports To: LLVM Dev <llvmdev at cs.uiuc.edu> Message-ID: <1317899647.25395.40.camel at csanchez-desktop> Content-Type: text/plain; charset="utf-8" Hi all, here is the current (unfinished) version of the VLIW support I mentioned. It i...

Hi all, is it possible to define an instruction as always having a certain register as operand in XXXInstrInfo.td? I know I can do it defining a single-register register class, but I need that register also to be on a broader class for other operations (and it is not possible for a reg to be in several classes AFAIU). Thanks! Carlos

Hi all, I have a pass that duplicates all instructions and keeps a "reference map" of duplicated values, which is later used to update all the references, thus creating a whole copy of a previous function. How I was doing it is calling "replaceUsesOfWith" in all the replicated instructions. This used to work on 2.9 and older, in svn it no longer does in the case of PHI nodes,

Hi all, we have release our (still quite in progress) OpenCL implementation. It uses a set of LLVM passes to statically replicate the workitems and generate a bytecode of the actual code to be run, taking into account the WI synchronization (barriers). >From the project description: Portable OpenCL is an open source implementation of the OpenCL standard which can be easily adapted for new

Hi all, I am finding a SEGFAULT in one of my passes when using getPrevNode on an instruction that is the only one in a BasicBlock. I was expecting getPrevNode to return 0 in that case (as per docs), but it breaks. I guess the code in in ilist_node.h: NodeTy *getPrevNode() { NodeTy *Prev = this->getPrev(); // Check for sentinel. if (!Prev->getNext()) return 0; return Prev; }

Hi people, the LinearScan register allocator tries to use same register for both live intervals, if the new interval is defined by a register copy whose destination reg is compatible with the source register. This is ok. However, this "check for compatibility" is wrongly done IMHO. Say I have regclass1 with reg A, and regclass2 with regs {A, B}, but regclass2 defines only

Hi, > Has anyone attempted the port of LLVM to a VLIW architecture? Is there > any publication about it? I have developed a derivation of MachineInstr class, called MachineInstrBundle, which is essnetially a VLIW-style machine instruction which can store any MI on each "slot". After the scheduling phase has grouped MIs in bundles, it has to call MIB->pack() method, which

Hi all, The machine I am targeting has some special requirements for some operations, say: ADD or1, ir1, r5 would add ir1 (input reg 1) and r5 and put the result in or1 (output reg 1). The point id that input and output regs have to go paired (this meaning an addition of ir1 with whatever always goes to or1, or an in general irX + whatever goes to orX). AFAIK, InstrInfo.td only allow

Hi Jakob, >> Say I have regclass1 with reg A, and regclass2 with regs {A, B}, but >> regclass2 defines only "B" as allocatable by RA. > > The register allocator assumes in many places that a register is > either allocatable or reserved independently of the register class. Is there any reason for this? I mean, the methods for allowing one physical reg be

Hi all, I am trying to replace all uses of a value1 *inside of a given function* to use value2. My strategy was to iterate all the basic blocks, again iterating all the instructions in each basic block, and using replaceUsesOfWith(value1, value2) for every instruction. This used to work all right, but now I am finding some problems. There are instructions like this: store i32 0, i32*

Hi all, We are working on a backend for a machine that has 4-wide vector register & ops, *but* not vector loads. All the vector register elements are directly accesible, so VI1 reg (Vector Integer 1) has I4, I5, I6 and I7 as its (integer) subregisters. Subregisters of same reg *never* overlap. Therefore, vector loads are lowered to scalar loads followed by a chain of INSERT_VECTOR_ELTs. Then

Hi Ralf, > The project started as a use-case for our "Whole-Function Vectorization" > library, which allows to transform a function to compute the same as W > executions of the original code by using SIMD instructions (W = 4 for > SSE/AltiVec, 8 for AVX). Quite interesting. We were planning to add "vectorization" to our passes also, but if I understood the