Displaying 4 results from an estimated 4 matches for "defs_macho".
2007 Feb 14
2
[LLVMdev] Linux/ppc backend
.....
Defs = [{
static const unsigned Defs_ELF[] =
{R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,
V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
LR,CTR,
CR0,CR1,CR5,CR6,CR7}
static const unsigned Defs_Macho[] =
{R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
LR,CTR,
CR0,CR1,CR5,CR6,CR7}
GPRClass::iterator
GPRClass::allocation_order_begin(const...
2007 Feb 15
0
[LLVMdev] Linux/ppc backend
...c const unsigned Defs_ELF[] =
> {R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
> F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,
>
> V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
> LR,CTR,
> CR0,CR1,CR5,CR6,CR7}
>
> static const unsigned Defs_Macho[] =
> {R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
> F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
>
> V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
> LR,CTR,
> CR0,CR1,CR5,CR6,CR7}
>
> GPRClass::iterator
> GPRClas...
2007 Feb 02
0
[LLVMdev] Linux/ppc backend
On Fri, 2 Feb 2007, Nicolas Geoffray wrote:
> I have almost completed the implementation of a linux/ppc backend in llvm.
Cool!
> There were a few things to modify in
> lib/Target/PowerPC with a lot of "if (!isDarwin)".
Some meta comments:
1. Please don't change PPC -> llvmPPC. I assume that you did this because
PPC is a #define in some system header. Please
2007 Feb 02
5
[LLVMdev] Linux/ppc backend
Hi everyone,
I have almost completed the implementation of a linux/ppc backend in
llvm. There were a few things to modify in
lib/Target/PowerPC with a lot of "if (!isDarwin)".
There are some places where I need help before saying the port is
complete. I attached the diff file as a reference
1) In order to generate a creqv instruction before a vararg call, I
created a new