search for: defreg

...emitting actual machine code. The target language has instructions that operate on pointers which aren't naturally exposed in LLVM. Here's what I've done to add pointer support for an instruction called PADD that takes a pointers and an offset and returns the new pointer value: def DefReg : Register<"r">; def PtrReg : Register<"ptr">; def I32RC : RegisterClass<"BE", [i32], 32, [DefReg]>; def P32RC : RegisterClass<"BE", [i32], 32, [PtrReg]>; def BEInst<bits<8> op, dag outs, dag ins, string asmstr, list<dag&gt...

..., AliasAnalysis *AA) const { const MachineFunction &MF = *MI.getParent()->getParent(); const MachineRegisterInfo &MRI = MF.getRegInfo(); // Remat clients assume operand 0 is the defined register. if (!MI.getNumOperands() || !MI.getOperand(0).isReg()) return false; unsigned DefReg = MI.getOperand(0).getReg(); // A sub-register definition can only be rematerialized if the instruction // doesn't read the other parts of the register. Otherwise it is really a // read-modify-write operation on the full virtual register which cannot be // moved safely. if (TargetRe...

...t language > has instructions that operate on pointers which aren't naturally > exposed > in LLVM. Here's what I've done to add pointer support for an > instruction > called PADD that takes a pointers and an offset and returns the new > pointer value: > > def DefReg : Register<"r">; > def PtrReg : Register<"ptr">; > def I32RC : RegisterClass<"BE", [i32], 32, [DefReg]>; > def P32RC : RegisterClass<"BE", [i32], 32, [PtrReg]>; > def BEInst<bits<8> op, dag outs, dag ins, string as...

...030, R1029 add_pointer R1031, R1025,R1028 // calculating the dst address store R1030, R1031 mov R1031, 4 add R1032, R1026, R1031 //scalar addition ret Currently my ADD instruction is defined in the InstrInfo.td file as following: def I32RC : RegisterClass<"MyMachine", [i32], 32, [DefReg]>; def P32RC : RegisterClass<"MyMachine", [iPTR], 32, [DefReg]>; -> I get error from tablegen if I use iPTR def MyAdd : MyInst < myadd, nosubop, (outs I32RC:$dst), (ins I32RC:$src1, I32RC:$src2), “add $dst, $src1, $src2", [(set rc:$dst, (add I32RC:$src1, I32RC:$...

...ructions that operate on pointers which aren't naturally >> exposed >> in LLVM. Here's what I've done to add pointer support for an >> instruction >> called PADD that takes a pointers and an offset and returns the new >> pointer value: >> >> def DefReg : Register<"r">; >> def PtrReg : Register<"ptr">; >> def I32RC : RegisterClass<"BE", [i32], 32, [DefReg]>; >> def P32RC : RegisterClass<"BE", [i32], 32, [PtrReg]>; >> def BEInst<bits<8> op, dag outs, d...

...030, R1029 add_pointer R1031, R1025,R1028 // calculating the dst address store R1030, R1031 mov R1031, 4 add R1032, R1026, R1031 //scalar addition ret Currently my ADD instruction is defined in the InstrInfo.td file as following: def I32RC : RegisterClass<"MyMachine", [i32], 32, [DefReg]>; def P32RC : RegisterClass<"MyMachine", [iPTR], 32, [DefReg]>; -> I get error from tablegen if I use iPTR def MyAdd : MyInst < myadd, nosubop, (outs I32RC:$dst), (ins I32RC:$src1, I32RC:$src2), “add $dst, $src1, $src2", [(set rc:$dst, (add I32RC:$src1, I32RC:$sr...

...SDTCisSameAs<0, 1>]>; def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem, [SDNPOutGlue]>; class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin, RegisterClass RC, list<Register> DefRegs>: FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), !strconcat(instr_asm, "\t$$zero, $rs, $rt"), [(op RC:$rs, RC:$rt)], itin> { let rd = 0; let shamt = 0; let Defs = DefRegs; } Note:,there doesn't seem to be an issue with the 32 bit versions which seem to be t...

hi cant get wine compiled, tried the wineinstall script as user, these are the last lines :( Preparing to install default Wine registry entries... Installing default Wine registry entries... ./wineinstall: line 648: 28561 Segmentation fault $REGEDIT $DEFREG >/dev/null Registry install failed. permissions of /dev/null are 777 any ideas are welcome ______________________________________________________________________________ Nachrichten, Musik und Spiele schnell und einfach per Quickstart im WEB.DE Screensaver - Gratis downloaden: http://screen...

...nters which aren't naturally >>> exposed >>> in LLVM. Here's what I've done to add pointer support for an >>> instruction >>> called PADD that takes a pointers and an offset and returns the new >>> pointer value: >>> >>> def DefReg : Register<"r">; >>> def PtrReg : Register<"ptr">; >>> def I32RC : RegisterClass<"BE", [i32], 32, [DefReg]>; >>> def P32RC : RegisterClass<"BE", [i32], 32, [PtrReg]>; >>> def BEInst<bits<8>...

...h a PHI, but since the register classes differ, the resulting code is wrong. I've managed to get around this by inserting a COPY in TailDuplication but I don't know what the proper fix is to this. In TailDuplicatePass::ProcessPHI: const TargetRegisterClass *RC = MRI->getRegClass(DefReg); + const TargetRegisterClass *SrcRC = MRI->getRegClass(SrcReg); + + // If the register class of the PHI src is wider than the PHI def + // then we can't just use PHI src instead of PHI def in the cloned + // instruction. Instead we insert a copy, copying the PHI src to a + // register...