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>Resources and latency are not tied. An instruction is mapped to a scheduling class. A scheduling class is mapped to a set of resources and a per-operand list of latencies. Thanks for your kind explanation. Our heuristic algorithm have needed the latency and the resource per operand to check resource conflicts per cycle. In order to support this with LLVM, I expected a per-operand list of

Hi JinGu, We currently have the ResourceCycles list to indicate the number of cpu cycles during which a resource is reserved. We could simply add a ResourceDelay with similar grammar. The MachineScheduler could be taught to keep track of the first and last time that a resource is reserved. Note that the MachineScheduler will work with the instruction itineraries if you choose to implement them.

On Feb 19, 2014, at 1:54 PM, jingu <jingu at codeplay.com> wrote: > Hi Andy, > > I am trying to schedule and packetize instructions for VLIW at post-RA > stage or final codegen stage, where code transformations are not allowed > any more, because hardware can not resolve resource conflict. There is a > simple example as following: > > ADD dest_reg1, src_reg1,

Hi Andy and all, I have a question about per-operand machine model. I am finding some relations between 'MCWriteLatencyEntry' and 'MCWriteProcResEntry'. For example, class InstTEST<..., InstrItinClass itin> : Instruction { let Itinerary = Itin; } // I assume this MI writes 2 registers. def TESTINST : InstTEST<..., II_TEST> // schedule info II_TEST:

On Mar 3, 2014, at 8:53 AM, Pierre-Andre Saulais <pierre-andre at codeplay.com> wrote: > Hi Andrew, > > We are currently using a custom model where scheduling information is attached to each MCInstrDesc through tablegen, and we're trying to move to one of LLVM's models. > > To expand on what JinGu mentioned, our target has explicit ports that are used to read and

On Mar 4, 2014, at 10:05 AM, Pete Cooper <peter_cooper at apple.com> wrote: > > On Mar 3, 2014, at 2:21 PM, Andrew Trick <atrick at apple.com> wrote: > >> >> On Mar 3, 2014, at 8:53 AM, Pierre-Andre Saulais <pierre-andre at codeplay.com> wrote: >> >>> Hi Andrew, >>> >>> We are currently using a custom model where

I've been researching the state of 'file alteration monitoring' technology on Linux. Famd uses dnotify to inefficently monitor a handful of directories. The replacement for dnotify is being worked on in the kenel and it's called inotify. If I understand it correctly and they get it finished, it would be an awesome addition to rsync. With it, you could run rsync to update a

A new intel-gpu-tools quarterly release is available with the following changes: Library changes: - Added helpers for launching external processes and capturing their outputs. (Abdiel Janulgue) - Increased max pipe count to 6 to support AMD GPUs. (Leo (Sunpeng) Li) - Various improvements for Chamelium support. (Paul Kocialkowski) - Added Coffeelake platform support. (Rodrigo Vivi, Anusha

Greetings, Following patches are intended to support SR-IOV capability in the Linux kernel. With these patches, people can turn a PCI device with the capability into multiple ones from software perspective, which will benefit KVM and achieve other purposes such as QoS, security, and etc. Major changes between v4 -> v5: 1, remove interfaces for PF driver to create sysfs entries (Matthew

Greetings, Following patches are intended to support SR-IOV capability in the Linux kernel. With these patches, people can turn a PCI device with the capability into multiple ones from software perspective, which will benefit KVM and achieve other purposes such as QoS, security, and etc. Major changes between v4 -> v5: 1, remove interfaces for PF driver to create sysfs entries (Matthew