Displaying 10 results from an estimated 10 matches for "defition".
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defintion
2014 Feb 18
2
[LLVMdev] Question about per-operand machine model
...that the 'WriteResourceID' field of 'MCWriteLatencyEntry' is for identifying the WriteResources of each defintion as commented on code. As you know, tablegen sets the 'WriteResourceID' field of 'MCWriteLatencyEntry' with 'WriteID' when the 'Write' of defition is referenced by a 'ReadAdvance'. If we always set this field with 'WriteID', it causes problem? I can see that 'ReadAdvance' only uses the 'WriteResourceID' field of 'MCWriteLatencyEntry' in 'computeOperandLatency' function. I think the pair of laten...
2014 Feb 19
2
[LLVMdev] Question about per-operand machine model
...eID' field of 'MCWriteLatencyEntry' is for identifying
>> the WriteResources of each defintion as commented on code. As you
>> know, tablegen sets the 'WriteResourceID' field of
>> 'MCWriteLatencyEntry' with 'WriteID' when the 'Write' of defition is
>> referenced by a 'ReadAdvance'. If we always set this field with
>> 'WriteID', it causes problem? I can see that 'ReadAdvance' only uses
>> the 'WriteResourceID' field of 'MCWriteLatencyEntry' in
>> 'computeOperandLatency'...
2014 Feb 28
2
[LLVMdev] Question about per-operand machine model
...CWriteLatencyEntry' is for identifying
>>>> the WriteResources of each defintion as commented on code. As you
>>>> know, tablegen sets the 'WriteResourceID' field of
>>>> 'MCWriteLatencyEntry' with 'WriteID' when the 'Write' of defition is
>>>> referenced by a 'ReadAdvance'. If we always set this field with
>>>> 'WriteID', it causes problem? I can see that 'ReadAdvance' only uses
>>>> the 'WriteResourceID' field of 'MCWriteLatencyEntry' in
>>>>...
2014 Feb 18
2
[LLVMdev] Question about per-operand machine model
Hi Andy and all,
I have a question about per-operand machine model. I am finding some
relations between 'MCWriteLatencyEntry' and 'MCWriteProcResEntry'.
For example,
class InstTEST<..., InstrItinClass itin> : Instruction {
let Itinerary = Itin;
}
// I assume this MI writes 2 registers.
def TESTINST : InstTEST<..., II_TEST>
// schedule info
II_TEST:
2014 Mar 03
2
[LLVMdev] Question about per-operand machine model
...is for identifying
>>>>>> the WriteResources of each defintion as commented on code. As you
>>>>>> know, tablegen sets the 'WriteResourceID' field of
>>>>>> 'MCWriteLatencyEntry' with 'WriteID' when the 'Write' of defition is
>>>>>> referenced by a 'ReadAdvance'. If we always set this field with
>>>>>> 'WriteID', it causes problem? I can see that 'ReadAdvance' only uses
>>>>>> the 'WriteResourceID' field of 'MCWriteLatencyEntry&...
2014 Mar 04
2
[LLVMdev] Question about per-operand machine model
...gt;>>>>>> the WriteResources of each defintion as commented on code. As you
>>>>>>>> know, tablegen sets the 'WriteResourceID' field of
>>>>>>>> 'MCWriteLatencyEntry' with 'WriteID' when the 'Write' of defition is
>>>>>>>> referenced by a 'ReadAdvance'. If we always set this field with
>>>>>>>> 'WriteID', it causes problem? I can see that 'ReadAdvance' only uses
>>>>>>>> the 'WriteResourceID' field of &...
2005 Mar 03
4
Steroids for Rsync!
I've been researching the state of 'file alteration monitoring'
technology on Linux. Famd uses dnotify to inefficently monitor a handful
of directories. The replacement for dnotify is being worked on in the
kenel and it's called inotify. If I understand it correctly and they get
it finished, it would be an awesome addition to rsync. With it, you
could run rsync to update a
2017 Oct 04
0
[ANNOUNCE] intel-gpu-tools 1.20
...tests/perf: print [un]slice freq and report reasons in debug
tests/perf: update print_reports to print context ID
tests/perf: add per context filtering test for gen8+
Rodrigo Vivi (8):
lib/cfl: Introduce Coffeelake platform definition.
lib/cnl: Introduce Cannonlake platform defition.
lib/cnl: Add Cannonlake PCI IDs for U-skus.
lib/cnl: Add Cannonlake PCI IDs for Y-skus.
lib/instdone: Add Gen10 support.
lib/intel_batchbuffer: Add Gen10 support for render_copy and gpgpu_fillfunc.
lib/i915_pciids.h: Organize cnl/cfl ids.
i915_pciids: Change a K...
2008 Oct 21
16
[PATCH 0/15 v5] PCI: Linux kernel SR-IOV support
Greetings,
Following patches are intended to support SR-IOV capability in the
Linux kernel. With these patches, people can turn a PCI device with
the capability into multiple ones from software perspective, which
will benefit KVM and achieve other purposes such as QoS, security,
and etc.
Major changes between v4 -> v5:
1, remove interfaces for PF driver to create sysfs entries (Matthew
2008 Oct 21
16
[PATCH 0/15 v5] PCI: Linux kernel SR-IOV support
Greetings,
Following patches are intended to support SR-IOV capability in the
Linux kernel. With these patches, people can turn a PCI device with
the capability into multiple ones from software perspective, which
will benefit KVM and achieve other purposes such as QoS, security,
and etc.
Major changes between v4 -> v5:
1, remove interfaces for PF driver to create sysfs entries (Matthew