Displaying 3 results from an estimated 3 matches for "defidx".
2015 Jan 08
4
[LLVMdev] Machine LICM and cheap instructions?
...itinerary is available, this means that all of the defined operands are available in at most 1 cycle. ARM overrides this, and provides this more-customized definition:
bool ARMBaseInstrInfo::
hasLowDefLatency(const InstrItineraryData *ItinData,
const MachineInstr *DefMI, unsigned DefIdx) const {
if (!ItinData || ItinData->isEmpty())
return false;
unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
if (DDomain == ARMII::DomainGeneral) {
unsigned DefClass = DefMI->getDesc().getSchedClass();
int DefCycle = ItinData->getOperandCycle(DefC...
2013 Apr 30
1
[LLVMdev] Instruction Scheduling - migration from v3.1 to v3.2
...uot; style of pipeline itineraries.
This is closest to the old behavior. If an itinerary is defined, you get to override two hooks:
virtual int TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
const MachineInstr *DefMI, unsigned DefIdx,
const MachineInstr *UseMI,
unsigned UseIdx) const;
virtual unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
const MachineIns...
2016 Jun 08
2
Instruction Itineraries: question about operand latencies
I overrode getInstrLatency and did some printing to see what is available
there. It looks like the registers are still virtual at that point when
getInstrLatency is called - is that correct? (we needed to make some
decisions based on actual registers that have been assigned since some
registers are reserved as address space pointers and we could vary the
latency based on which address space