search for: defaultdeflatency

I'm unclear how does DFAPacketizer and the scheduler know a given instruction is a load. Here is what I'm talking about Let's assume my VLIW target is described as follows: def MyTargetItineraries : ProcessorItineraries<[Slot0, Slot1], [], [ .............................. InstrItinData<RI, [InstrStage<1, [Slot0, Slot1]>]>,

...interface to the machine model. It is not extensible. Instead, it checks the current subtarget configuration, and either directly queries latency tables, or calls hooks. Three possible configurations are: (1) No per-opcode tables In this case, only one helper is used: unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel *SchedModel, const MachineInstr *DefMI) const; This is currently non-virtual because it is designed to directly query the fields in the SchedMachineModel tablegen class using another hook to select high latency ops: virtual bool isHig...

> In particular, the LoadLatency is used in defaultDefLatency: > > /// Return the default expected latency for a def based on it's opcode. > unsigned TargetInstrInfo::defaultDefLatency( > const MCSchedModel &SchedModel, const MachineInstr *DefMI) const { > if (DefMI->isTransient()) > return 0; > if (DefMI->mayLo...