Displaying 4 results from an estimated 4 matches for "decq".
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dec
2011 Dec 22
1
[LLVMdev] tail call optimization question
...## @ack.15
Leh_func_begin1:
## BB#0: ## %entry
pushq %rbx
Ltmp1:
Ltmp2:
testq %rdi, %rdi
jle LBB1_3
## BB#1: ## %if.no
movq %rdi, %rbx
testq %rsi, %rsi
jle LBB1_4
## BB#2: ## %if.no2
decq %rsi
movq %rbx, %rdi
callq _ack.15
movq %rbx, %rdi
decq %rdi
movq %rax, %rsi
popq %rbx
jmp _ack.15 ## TAILCALL
LBB1_3: ## %if.yes
incq %rsi
movq %rsi, %rax
popq %rbx
ret
LBB1_4: ## %if.yes1
movq %rbx, %rdi...
2014 Feb 19
2
[LLVMdev] better code for IV
...# =>This Inner Loop Header: Depth=1
movq %r9, %rax
sarq $32, %rax
movss (%rdi,%rax,4), %xmm0
addss (%rsi,%rax,4), %xmm0
movss %xmm0, (%rdx,%rax,4)
addq %r8, %r9
decq %rcx
jne .LBB0_1
# BB#2:
Ret
This is what I want to get:
ArrayAdd2: # @ArrayAdd2
.cfi_startproc
# BB#0: # %Entry
xorl %eax, %eax
.align 16, 0x90
.LBB1...
2010 May 29
1
[LLVMdev] Vectorized LLVM IR
On Sat, May 29, 2010 at 1:18 AM, Eli Friedman <eli.friedman at gmail.com> wrote:
> On Sat, May 29, 2010 at 12:42 AM, Stéphane Letz <letz at grame.fr> wrote:
>>
>> Le 29 mai 2010 à 01:08, Bill Wendling a écrit :
>>
>>> Hi Stéphane,
>>>
>>> The SSE support is the LLVM backend is fine. What is the code that's generated? Do you have some
2013 Oct 15
0
[LLVMdev] [llvm-commits] r192750 - Enable MI Sched for x86.
...lsr-loop-exit-cond.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/lsr-loop-exit-cond.ll Tue Oct 15 18:33:07 2013
>> @@ -2,12 +2,12 @@
>> ; RUN: llc -mtriple=x86_64-darwin -mcpu=atom < %s | FileCheck -check-prefix=ATOM %s
>>
>> ; CHECK-LABEL: t:
>> -; CHECK: decq
>> -; CHECK-NEXT: movl (%r9,%rax,4), %eax
>> +; CHECK: movl (%r9,%rax,4), %e{{..}}
>> +; CHECK-NEXT: decq
>> ; CHECK-NEXT: jne
>>
>> ; ATOM-LABEL: t:
>> -; ATOM: movl (%r9,%r{{.+}},4), %eax
>> +; ATOM: movl (%r9,%r{{.+}},4), %e{{..}}
>> ; ATOM-...