Displaying 8 results from an estimated 8 matches for "dec_num_dev".
2013 Aug 12
1
[PATCH v2 1/7] Intel MIC Host Driver for X100 family.
...;
No locking, please use the idr interface...
> +
> + snprintf(name, sizeof(name), "mic%d", rc);
> + mdev = kzalloc(sizeof(*mdev), GFP_KERNEL);
> + if (!mdev) {
> + rc = -ENOMEM;
> + dev_err(&pdev->dev, "dev kmalloc failed rc %d\n", rc);
> + goto dec_num_dev;
> + }
> + strncpy(mdev->name, name, sizeof(name));
> + mdev->id = rc;
> +
> + mic_device_init(mdev, pdev);
> +
> + rc = pci_enable_device(pdev);
> + if (rc) {
> + dev_err(&pdev->dev, "failed to enable pci device.\n");
> + goto free_device;
>...
2013 Aug 12
1
[PATCH v2 1/7] Intel MIC Host Driver for X100 family.
...;
No locking, please use the idr interface...
> +
> + snprintf(name, sizeof(name), "mic%d", rc);
> + mdev = kzalloc(sizeof(*mdev), GFP_KERNEL);
> + if (!mdev) {
> + rc = -ENOMEM;
> + dev_err(&pdev->dev, "dev kmalloc failed rc %d\n", rc);
> + goto dec_num_dev;
> + }
> + strncpy(mdev->name, name, sizeof(name));
> + mdev->id = rc;
> +
> + mic_device_init(mdev, pdev);
> +
> + rc = pci_enable_device(pdev);
> + if (rc) {
> + dev_err(&pdev->dev, "failed to enable pci device.\n");
> + goto free_device;
>...
2013 Aug 08
0
[PATCH v2 1/7] Intel MIC Host Driver for X100 family.
...+{
+ int rc;
+ struct mic_device *mdev;
+ char name[20];
+
+ rc = g_mic.next_id++;
+
+ snprintf(name, sizeof(name), "mic%d", rc);
+ mdev = kzalloc(sizeof(*mdev), GFP_KERNEL);
+ if (!mdev) {
+ rc = -ENOMEM;
+ dev_err(&pdev->dev, "dev kmalloc failed rc %d\n", rc);
+ goto dec_num_dev;
+ }
+ strncpy(mdev->name, name, sizeof(name));
+ mdev->id = rc;
+
+ mic_device_init(mdev, pdev);
+
+ rc = pci_enable_device(pdev);
+ if (rc) {
+ dev_err(&pdev->dev, "failed to enable pci device.\n");
+ goto free_device;
+ }
+
+ pci_set_master(pdev);
+
+ rc = pci_request_re...
2013 Jul 25
0
[PATCH 1/5] Intel MIC Host Driver for X100 family.
...+{
+ int rc;
+ struct mic_device *mdev;
+ char name[20];
+
+ rc = g_mic.next_id++;
+
+ snprintf(name, sizeof(name), "mic%d", rc);
+ mdev = kzalloc(sizeof(*mdev), GFP_KERNEL);
+ if (!mdev) {
+ rc = -ENOMEM;
+ dev_err(&pdev->dev, "dev kmalloc failed rc %d\n", rc);
+ goto dec_num_dev;
+ }
+ strncpy(mdev->name, name, sizeof(name));
+ mdev->id = rc;
+
+ mic_device_init(mdev, pdev);
+
+ rc = pci_enable_device(pdev);
+ if (rc) {
+ dev_err(&pdev->dev, "failed to enable pci device.\n");
+ goto uninit_device;
+ }
+
+ pci_set_master(pdev);
+
+ rc = pci_request_...
2013 Aug 08
10
[PATCH v2 0/7] Enable Drivers for Intel MIC X100 Coprocessors.
ChangeLog:
=========
v1 => v2:
a) License wording cleanup, sysfs ABI documentation, patch 1 refactoring
into 3 smaller patches and function renames, as per feedback from
Greg Kroah-Hartman.
b) Use VRINGH infrastructure for accessing virtio rings from the host
in patch 5, as per feedback from Michael S. Tsirkin.
v1: Initial post @ https://lkml.org/lkml/2013/7/24/810
Description:
2013 Aug 08
10
[PATCH v2 0/7] Enable Drivers for Intel MIC X100 Coprocessors.
ChangeLog:
=========
v1 => v2:
a) License wording cleanup, sysfs ABI documentation, patch 1 refactoring
into 3 smaller patches and function renames, as per feedback from
Greg Kroah-Hartman.
b) Use VRINGH infrastructure for accessing virtio rings from the host
in patch 5, as per feedback from Michael S. Tsirkin.
v1: Initial post @ https://lkml.org/lkml/2013/7/24/810
Description:
2013 Jul 25
16
[PATCH 0/5] Enable Drivers for Intel MIC X100 Coprocessors.
An Intel MIC X100 device is a PCIe form factor add-in coprocessor
card based on the Intel Many Integrated Core (MIC) architecture
that runs a Linux OS. It is a PCIe endpoint in a platform and therefore
implements the three required standard address spaces i.e. configuration,
memory and I/O. The host OS loads a device driver as is typical for
PCIe devices. The card itself runs a bootstrap after
2013 Jul 25
16
[PATCH 0/5] Enable Drivers for Intel MIC X100 Coprocessors.
An Intel MIC X100 device is a PCIe form factor add-in coprocessor
card based on the Intel Many Integrated Core (MIC) architecture
that runs a Linux OS. It is a PCIe endpoint in a platform and therefore
implements the three required standard address spaces i.e. configuration,
memory and I/O. The host OS loads a device driver as is typical for
PCIe devices. The card itself runs a bootstrap after