Displaying 5 results from an estimated 5 matches for "deadnod".
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dead_node
2010 Oct 02
1
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
...()<< "\nReplacing.8 ";
>> TheXor->dump(&DAG);
>> dbgs()<< "\nWith: ";
>> Tmp.getNode()->dump(&DAG);
>> dbgs()<< '\n');
>> WorkListRemover DeadNodes(*this);
>> DAG.ReplaceAllUsesOfValueWith(N1, Tmp,&DeadNodes);
>> removeFromWorkList(TheXor);
>> DAG.DeleteNode(TheXor);
>> return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
>> MVT::Other, Chain, T...
2010 Sep 30
4
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
...mp.getNode() != TheXor) {
DEBUG(dbgs() << "\nReplacing.8 ";
TheXor->dump(&DAG);
dbgs() << "\nWith: ";
Tmp.getNode()->dump(&DAG);
dbgs() << '\n');
WorkListRemover DeadNodes(*this);
DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes);
removeFromWorkList(TheXor);
DAG.DeleteNode(TheXor);
return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
MVT::Other, Chain, Tmp, N2);
}
}
if (Op0.getOp...
2010 Oct 01
0
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
...{
> DEBUG(dbgs() << "\nReplacing.8 ";
> TheXor->dump(&DAG);
> dbgs() << "\nWith: ";
> Tmp.getNode()->dump(&DAG);
> dbgs() << '\n');
> WorkListRemover DeadNodes(*this);
> DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes);
> removeFromWorkList(TheXor);
> DAG.DeleteNode(TheXor);
> return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
> MVT::Other, Chain, Tmp, N2);
> }
&g...
2010 Sep 29
0
[LLVMdev] comparison pattern trouble - might be a bug in LLVM 2.8?
On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote:
> On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
>
>> Our architecture has 1-bit boolean predicate registers.
>>
>> I've defined comparison
>>
>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;
2010 Sep 29
1
[LLVMdev] comparison pattern trouble - might be a bug in LLVM 2.8?
On 29 Sep 2010, at 06:25, Heikki Kultala wrote:
> Our architecture has 1-bit boolean predicate registers.
>
> I've defined comparison
>
>
> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;
>
>
>
>
> But then I end up having the following bug:
>
>