search for: dcpu

Hi. I'm working on a backend for the [DCPU16](https://github.com/techcompliant/TC-Specs/blob/master/CPU/DCPU.md), a fictional CPU. The main subtlety is that the bytes are 16 bits instead of 8. There is already a [working backend](https://github.com/krasin/llvm-dcpu16), but it does a lot of source modification to support 16 bit words. I...

...power-of-two bit widths) fully, and therefore not able to submit it upstream. One idea we have toyed with is to create a simple "dummy" version of our target, just to be able complement patches with tests. For 16-bit byte support we may also pick some existing simple architecture, such as DCPU-16 or TI C54x. One other idea is just to have the changes on a branch upstream. /Patrik Hägglund From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Reid Kleckner Sent: den 10 mars 2015 17:09 To: Tyro Software Cc: LLVM Developers Mailing List Subject: Re: [LL...

Back in 2009 there was some discussion of the practicality of supporting char sizes greater than 8-bit: http://lists.cs.uiuc.edu/pipermail/cfe-dev/2009-September/thread.html#6349 http://lists.cs.uiuc.edu/pipermail/llvmdev/2009-September/thread.html#26025 with the consensus seemingly being "quite doable, please get a good patch and submit". However the current code appears (to my

The PNaCl project has implemented various IR simplification passes that simplify LLVM IR by lowering complex features to simpler features. We'd like to upstream some of these IR passes to LLVM. We'd like to explore if this acceptable, and if so, how we should go about doing this. The immediate reason is that Emscripten is reusing PNaCl's IR passes for its new "fastcomp"