search for: dcbtst

...hat is done with cache levels to express this kind > of sharing. We haven't found a need for it but that doesn't mean it > wouldn't be useful for other/new targets. The example above is IBM's Blue Gene/Q processor, so yes, such targets do exist. > > PowerPC's dcbt/dcbtst instruction allows explicitly specifying to the > > hardware which streams it should establish. Do the buffer counts > > include explicitly and automatically established streams? Do > > non-stream accesses (e.g. stack access) count towards > > It's up to the target maint...

...What count's as steam? Some processors may support streams with strides and/or backward stream. Is there a way on which level the number of streams are shared? For instance, a core might be able to track 16 streams, but if 4 threads are running (SMT), each can only use 4. PowerPC's dcbt/dcbtst instruction allows explicitly specifying to the hardware which streams it should establish. Do the buffer counts include explicitly and automatically established streams? Do non-stream accesses (e.g. stack access) count towards > class TargetMemorySystemInfo { > const TargetCacheLevel...