search for: daniel_l_sand

Displaying 20 results from an estimated 72 matches for "daniel_l_sand".

2017 Sep 18
1
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...hat we need the opposite - if (.. < 8) getExtLoad // VT should be MVT::i8, MemVT should be MVT::i1 else getLoad - Elena From: jingu at codeplay.com [mailto:jingu at codeplay.com] Sent: Monday, September 18, 2017 13:40 To: Demikhovsky, Elena <elena.demikhovsky at intel.com>; daniel_l_sanders at apple.com <daniel_l_sanders at apple.com>; Jon Chesterfield <jonathanchesterfield at gmail.com> Cc: llvm-dev at lists.llvm.org Subject: Re: Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT' um... In order to reproduce the issue, we need to add 'i1'...
2017 May 31
2
Buildbots timing out on full builds
...030s > > (on top of a fully built r303542). It should be fine for the ARM bots. > > However, you need to 'return std::move(M)' at line 1884. > > @Vitaly, is it ok for your bots as well? > > Cheers, > Diana > > On 31 May 2017 at 10:21, Daniel Sanders <daniel_l_sanders at apple.com <mailto:daniel_l_sanders at apple.com>> wrote: > Hi Diana and Vitaly, > > Could you give https://reviews.llvm.org/differential/diff/100829/ <https://reviews.llvm.org/differential/diff/100829/> a try? When measuring the compile of AArch64InstructionSelector.c...
2017 Sep 17
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
Please open a bugzilla ticket and attach your testcase. It will allow us to debug and fix the problem. Thanks - Elena From: JinGu [mailto:jingu at codeplay.com] Sent: Saturday, September 16, 2017 00:38 To: Demikhovsky, Elena <elena.demikhovsky at intel.com>; daniel_l_sanders at apple.com <daniel_l_sanders at apple.com>; Jon Chesterfield <jonathanchesterfield at gmail.com> Cc: llvm-dev at lists.llvm.org Subject: Re: Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT' Hi Elena, Thanks for your response. The store is ok but the exten...
2017 May 31
0
Buildbots timing out on full builds
...ntial/diff/100829/ replacement for r303341? If so LGTM. r303542 msan AArch64InstructionSelector.cpp: 1m17.209s r303542+diff/100829/ <https://reviews.llvm.org/differential/diff/100829/> msan AArch64InstructionSelector.cpp: 1m24.724s On Wed, May 31, 2017 at 6:13 AM, Daniel Sanders <daniel_l_sanders at apple.com> wrote: > Great! I expect I'll be able to cut it down further once I start fusing > these smaller state-machines together. Before that, I'll re-order the > patches that went into that diff so that I don't have to re-commit the > regression before fixing i...
2018 Dec 06
3
New to LLVM. Need help generating assembly
> On Dec 5, 2018, at 22:15, Tom Stellard via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > On 12/05/2018 07:22 PM, m m via llvm-dev wrote: >> Hi, >> I'm new to LLVM and need some help. I defined an instruction to increment the stack pointer by 'amount' (i.e. sp = sp + amount). During assembly generation, the string that gets emitted is "ADS $SP"
2017 May 31
2
Buildbots timing out on full builds
...hopefully sufficient to unblock my patch series. > On 26 May 2017, at 09:10, Diana Picus <diana.picus at linaro.org> wrote: > > Ok, that sounds reasonable. I'm happy to test more patches for you > when they're ready. > > On 25 May 2017 at 17:39, Daniel Sanders <daniel_l_sanders at apple.com> wrote: >> Thanks for trying that patch. I agree that 34 mins still isn't good enough but we're heading in the right direction. >> >> Changing the partitioning predicate to the instruction opcode rather than the number of operands in the top-level instr...
2020 Sep 30
2
Relation between Register and MCRegister
> On 29 Sep 2020, at 11:13, Mircea Trofin <mtrofin at google.com> wrote: > > > > On Tue, Sep 29, 2020 at 11:09 AM Daniel Sanders <daniel_l_sanders at apple.com <mailto:daniel_l_sanders at apple.com>> wrote: > Yes so long as you're including the invalid space too (IIRC it matters for DBG_VALUE in particular) the reason I didn't do that is that there's a lot more ctors than consumers of MCRegister. It seemed cheaper t...
2017 May 24
2
Buildbots timing out on full builds
...ction. This constrains the scale of the task the > register allocator needs to deal with in X86InstructionSelection.cpp.o. > > On 22 May 2017, at 10:42, Diana Picus <diana.picus at linaro.org> wrote: > > Nope, no sanitizers. > > On 22 May 2017 at 11:38, Daniel Sanders <daniel_l_sanders at apple.com> > wrote: > > Is that with -fsanitize=memory too? > > I'm currently building ToT with r303258 reverted. Once that's done I'll > commit the revert and start investigating fixes. > > On 22 May 2017, at 10:22, Diana Picus <diana.picus at linaro...
2017 May 22
2
Buildbots timing out on full builds
Nope, no sanitizers. On 22 May 2017 at 11:38, Daniel Sanders <daniel_l_sanders at apple.com> wrote: > Is that with -fsanitize=memory too? > > I'm currently building ToT with r303258 reverted. Once that's done I'll commit the revert and start investigating fixes. > >> On 22 May 2017, at 10:22, Diana Picus <diana.picus at linaro.org> wr...
2017 May 22
4
Buildbots timing out on full builds
...s user 35m37.091s sys 0m44.726s and for r303259: real 50m52.048s user 88m25.473s sys 0m46.548s If I can help investigate, please let me know, otherwise we can just try your fixes and see how they affect compilation time. Thanks, Diana On 22 May 2017 at 10:49, Daniel Sanders <daniel_l_sanders at apple.com> wrote: > r303341 is the re-commit of the r303259 which tripled the number of rules > that can be imported into GlobalISel from SelectionDAG. A compile time > regression is to be expected but when I looked into it I found it was ~25s > on my machine for the whole incr...
2018 Jan 04
2
Canonical way to handle zero registers?
On Tue, Jan 2, 2018 at 8:28 AM, Daniel Sanders <daniel_l_sanders at apple.com> wrote: > Hi Sean, > > Just to give the GlobalISel perspective on this, Thanks for chiming in! > GlobalISel supports the declaration of a zero register in the register > class like so: > def GPR32z : RegisterOperand<GPR32> { > let...
2017 Aug 21
3
RFC/bikeshedding: Separation of instruction and pattern definitions in LLVM backends
On 21 August 2017 at 11:53, Daniel Sanders <daniel_l_sanders at apple.com> wrote: > One thing to be aware of with this is that (IIRC) tablegen uses the pattern to infer things about the pattern. One example I vaguely remember is that an empty pattern would result in the same effect as hasSideEffects=1 and I think there were others. Thanks for the n...
2017 Sep 15
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
...on stack. Store is responsible for zero-extend. This is the policy... - Elena -----Original Message----- From: jingu at codeplay.com [mailto:jingu at codeplay.com] Sent: Friday, September 15, 2017 17:45 To: llvm-dev at lists.llvm.org; Demikhovsky, Elena <elena.demikhovsky at intel.com>; daniel_l_sanders at apple.com Subject: Re: Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT' Can someone give the comment about it please? Thanks, JinGu Kang On 14/09/17 12:05, jingu at codeplay.com wrote: > Hi All, > > I have a question about splitting 'EXTRACT_VECTOR_EL...
2018 Jan 04
0
Canonical way to handle zero registers?
> On 3 Jan 2018, at 19:44, Sean Silva <chisophugis at gmail.com> wrote: > > > On Tue, Jan 2, 2018 at 8:28 AM, Daniel Sanders <daniel_l_sanders at apple.com <mailto:daniel_l_sanders at apple.com>> wrote: > Hi Sean, > > Just to give the GlobalISel perspective on this, > > Thanks for chiming in! > > GlobalISel supports the declaration of a zero register in the register class like so: > def GPR3...
2020 Sep 29
2
Relation between Register and MCRegister
...ircea Trofin <mtrofin at google.com> wrote: > > Thanks! To test my understanding - we could add asserts in MCRegister ctor that the value of the unsigned is, indeed, only in the physical register namespace, is that correct? > > On Tue, Sep 29, 2020 at 10:49 AM Daniel Sanders <daniel_l_sanders at apple.com <mailto:daniel_l_sanders at apple.com>> wrote: > > >> On 29 Sep 2020, at 09:28, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote: >> >> + Daniel who added the MCRegister class. >> >> Ah sorry...
2017 May 25
2
Buildbots timing out on full builds
...88m25.473s >> sys 0m46.548s >> >> If I can help investigate, please let me know, otherwise we can just >> try your fixes and see how they affect compilation time. >> >> Thanks, >> Diana >> >> On 22 May 2017 at 10:49, Daniel Sanders <daniel_l_sanders at apple.com> wrote: >>> r303341 is the re-commit of the r303259 which tripled the number of rules >>> that can be imported into GlobalISel from SelectionDAG. A compile time >>> regression is to be expected but when I looked into it I found it was ~25s >>>...
2017 Aug 25
3
llvm-mc-[dis]assemble-fuzzer status?
On Fri, Aug 25, 2017 at 8:51 AM, Daniel Sanders <daniel_l_sanders at apple.com> wrote: > (removed my @imgtec.com address since it no longer exists) > > Sorry for the slow reply, it's a busy time for me right now. > > > On 23 Aug 2017, at 00:21, George Karpenkov via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > &gt...
2018 Nov 03
2
mips builders on LLVM buildbot?
Hi Galina, I will try to find owners of these buildbots. I hope to get results on the next week. On Sat, Nov 3, 2018 at 1:48 AM Daniel Sanders <daniel_l_sanders at apple.com> wrote: > > Hi Galina, > > I'm sad that they appear to have been abandoned but no objections from me as I'm not the admin for any of these anymore. A couple of them were taken over by a colleague when I left but he too has left MIPS since then. Simon Atanasyan...
2017 Nov 11
2
RFC: [GlobalISel] Towards a generic MI combiner framework
...e use-count checks won't do the right thing (because the old unused uses of things won't immediately go away). I'm not entirely sure you can just turn off the uniquing in SDAG and get a sensible result. -Hal > >> On Nov 10, 2017, at 9:54 PM, Daniel Sanders >> <daniel_l_sanders at apple.com <mailto:daniel_l_sanders at apple.com>> wrote: >> >> My thinking on this is that (with a few exceptions that I'll get to), >> combine and select are basically the same thing. You match some MIR, >> and replace it with other MIR. The main differ...
2017 May 21
2
Buildbots timing out on full builds
...orresponding llvm-commits thread. On Fri, May 19, 2017 at 7:34 AM, Diana Picus via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Ok, thanks. I'll try to do a bisect next week to see if I can find it. > > Cheers, > Diana > > On 19 May 2017 at 16:29, Daniel Sanders <daniel_l_sanders at apple.com> > wrote: > > > >> On 19 May 2017, at 14:54, Daniel Sanders via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> > >> r303259 will have increased compile-time since it tripled the number of > importable > >> SelectionDA...