search for: dagbuild

Hi, How can I get the llvm-type of the formal argument while lowering it ? My target needs to map pointer and non-pointer parameters to different registers. In addition, parameter lowering is address space dependent (another reason why I need such information). Looking at the DAGBuilder, I found that it is dropping it when translating llvm-types to BE types. Even if the base type is saved into the MVT structure, it's a private member. What's the reason for hiding it ? Why not to keep such information ? Thanks in advance, Ivan

...to model, function attributes can be used but they would apply to the whole function (or specific arguments). It may also be possible to use an intrinsic to mark the pointer itself instead of the instructions manipulating it, again it depends on what you are modelling. I've found that in the DAGBuilder metadata information connected with > LoadInst instruction is utilized: > bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != > nullptr; > > Is this metadata somehow protected against dropping - as you mentioned? > Nothing is protected as far as I know, the desi...

I'm trying to 'lower' an operation that needs to create a node in the SD that is an intrinsic call.... what is the best way to do this? I see in the DAGBuilder it calls 'setValue' which adds to the map NodeMap[V] where V is the key and the passed in SDValue is the value but I'm not sure this is a good way to do it since these are local to SelectionDAGBuilder and the lowering needs to happen in XXXISelLowering.cpp. Thanks. -------------- nex...

...ring DAG Instruction Selection in order to match given >> pattern based on this marking. >> >> >> >> I’m wondering if marking IR instruction utilizing Metadata is good idea. >> >> But how later pass that information to DAG and appropriately mark in >> DAGBuilder SDNode, which represents the earlier marked instruction in IR? >> >> >> >> Any suggestion how to implement the most efficiently? >> >> I’m expecting there are already similar solutions – maybe someone would >> be able to indicate the exact example? >&g...

...uction during IR custom pass and later utilizing that information during DAG Instruction Selection in order to match given pattern based on this marking. I’m wondering if marking IR instruction utilizing Metadata is good idea. But how later pass that information to DAG and appropriately mark in DAGBuilder SDNode, which represents the earlier marked instruction in IR? Any suggestion how to implement the most efficiently? I’m expecting there are already similar solutions – maybe someone would be able to indicate the exact example? Thanks in advance, Przemek -------------- next part ---------...

...; > How can I get the llvm-type of the formal argument while lowering it ? > > My target needs to map pointer and non-pointer parameters to different > registers. In addition, parameter lowering is address space dependent > (another reason why I need such information). Looking at the DAGBuilder, > I found that it is dropping it when translating llvm-types to BE types. > Even if the base type is saved into the MVT structure, it's a private > member. What's the reason for hiding it ? Why not to keep such information ? > > Thanks in advance, > > Ivan > _____...

Hi, In the directory of lib/CodeGen/SelectionDAG, I cann't find SelectionDAGISel.cpp. I only have DAGBuilder.cpp and SelectionDAG.cpp. I don't know why. My edtion is 1.4. Is it because of the edtion difference? Thanks! > On Mon, 11 Jul 2005 shding at mtu.edu wrote: >> I have extended the IR for adding flag. But I just want this flag to >> pass through the backend machine code. I k...

...get the llvm-type of the formal argument while lowering it ? >> >> My target needs to map pointer and non-pointer parameters to different >> registers. In addition, parameter lowering is address space dependent >> (another reason why I need such information). Looking at the DAGBuilder, >> I found that it is dropping it when translating llvm-types to BE types. >> Even if the base type is saved into the MVT structure, it's a private >> member. What's the reason for hiding it ? Why not to keep such information ? >> >> Thanks in advance, >&...

...field lookups as well. Add type codes into bitreader/bitwriter which would cope with the new union type. Add u { ... } into the AsmParser. Revise some of the target classes to cope with the unusual data layout and report back correct size for the union type. Add support for DAG generation into the DAGBuilder visitor class. I am just seeing this UnionType as a type of struct where all the fields have the same offset and the UnionType itself is as large as the largest member. I would speculate that otherwise it behaves pretty much like a StructType- but then again I am new to LLVM. --- On Sun, 8/2/0...

...brief overview for reference: An instruction in the LLVM IR gets converted into an SDNode in the DAG then later into a MachineInstr. I'd already attached my own MDNodes to IR instructions I was interested in. I wanted to propagate that info to the final binary. I Added a field to the SelectionDAGBuilder holding the current metadata which I update in SelectionDAGISel::SetDebugLoc() for every IR instruction. Next, in SelectionDAGBuilder::visit() i transfer the current instruction's metadata from the DAGBuilder to the instruction's SDNode. In InstrEmitter::EmitNode() I copy the metadata f...

...itreader/bitwriter > which would cope with the new union type. Add u { ... } into > the AsmParser. > > > > Revise some of the target classes to cope with the > unusual data layout and report back correct size for the > union type. Add support for DAG generation into the > DAGBuilder visitor class. > > > > I am just seeing this UnionType as a type of struct > where all the fields have the same offset and the UnionType > itself is as large as the largest member. I would speculate > that otherwise it behaves pretty much like a StructType- but > then agai...

...kups as well. Add type codes into bitreader/bitwriter which would cope with the new union type. Add u { ... } into the AsmParser. > > Revise some of the target classes to cope with the unusual data layout and report back correct size for the union type. Add support for DAG generation into the DAGBuilder visitor class. > > I am just seeing this UnionType as a type of struct where all the fields have the same offset and the UnionType itself is as large as the largest member. I would speculate that otherwise it behaves pretty much like a StructType- but then again I am new to LLVM. > >...

...which would cope with the new union type. Add u { ... } into >> the AsmParser. >> > >> > Revise some of the target classes to cope with the >> unusual data layout and report back correct size for the >> union type. Add support for DAG generation into the >> DAGBuilder visitor class. >> > >> > I am just seeing this UnionType as a type of struct >> where all the fields have the same offset and the UnionType >> itself is as large as the largest member. I would speculate >> that otherwise it behaves pretty much like a StructType...

...get the llvm-type of the formal argument while lowering it ? >> >> My target needs to map pointer and non-pointer parameters to different >> registers. In addition, parameter lowering is address space dependent >> (another reason why I need such information). Looking at the DAGBuilder, >> I found that it is dropping it when translating llvm-types to BE types. >> Even if the base type is saved into the MVT structure, it's a private >> member. What's the reason for hiding it ? Why not to keep such information ? >> >> Thanks in advance, >&...

On Saturday, March 4, 2017, Ryan Taylor <ryta1203 at gmail.com> wrote: > Why you can't still expand it through MUL with a Custom lowering? Or am I > missing something? > > Yes we can but problem occurs when we know that it is shift with constant value than if we return ISD::MUL with constant imm operand than LLVM will convert it to SHL again because the constant will be

...b 2, 2016, at 09:29, Ryan Taylor via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > > I'm trying to 'lower' an operation that needs to create a node in the SD > that is an intrinsic call.... what is the best way to do this? > > > > I see in the DAGBuilder it calls 'setValue' which adds to the map > NodeMap[V] where V is the key and the passed in SDValue is the value but > I'm not sure this is a good way to do it since these are local to > SelectionDAGBuilder and the lowering needs to happen in XXXISelLowering.cpp. > > &g...

Hello, My understanding of the discussions about union types was that there was trouble working out how unions should work. Have the issues been resolved? If so, could you post a summary? Thanks, Dan On Aug 2, 2009, at 7:45 AM, Carter Cheng wrote: > I am curious how the efforts were progressing in implementing a > union type. I am will to try to contribute somewhat to this even

On Mon, 11 Jul 2005 shding at mtu.edu wrote: > I have extended the IR for adding flag. But I just want this flag to > pass through the backend machine code. I know there're several passes > like register relocation, schedualing, etc. But I think I just miss the > part which is used to "parser" the LLVM IR to machine code > instructions. The part of the code

I am curious how the efforts were progressing in implementing a union type. I am will to try to contribute somewhat to this even though I am perhaps somewhat of a beginner with LLVM(so it might be nice to collaborate with someone). I had a look at some of the subsystems that would require changes though I may have missed some. I however have a few questions- 1) What is ComputeLinearIndex for

Drear there: The problem I have is to lower an intrinsic function like this ” float @llvm.write.arg(flaot %src, float* %dst) “ I am lowering it with INTRINSIC_W_CHAIN, so the return value and the value to write to dst are generated with some operations using src: " // it is the frame index node corresponding to input pointer SDvalue frindex = Op.getoperand(3); … SDValue returnValue =