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2018 Sep 06
3
How to add Loongson ISA for Mips target?
...p,48,$31 # vars= 16, regs= 3/0, args= 0, gp= 0
.mask 0xd0000000,-8
.fmask 0x00000000,0
.set noreorder
.set nomacro
daddiu $sp,$sp,-48
gssq $31,$fp,32($sp)
sd $28,24($sp)
move $fp,$sp
lui $28,%hi(%neg(%gp_rel(main)))
daddu $28,$28,$25
daddiu $28,$28,%lo(%neg(%gp_rel(main)))
move $2,$4
sd $5,8($fp)
sll $2,$2,0
sw $2,0($fp)
ld $2,%got_page(.LC0)($28)
daddiu $4,$2,%got_ofst(.LC0)
ld $2,%call16(puts)($28)
move $25,$2
.reloc 1f,R_MIPS_JALR,...
2014 Apr 29
2
[LLVMdev] MIPS n64 ABI and non-PIC
Has anyone experimented with generating non-PIC for MIPS64 and the n64 ABI?
Currently MipsISelLowering.cpp uses conditions like:
if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || IsN64) {
}
around any PIC code generation. Is generating non-PIC just untested, or is
it known not to work? I can't find any discussion of it anywhere. I ran
into this when trying to see why
2014 May 02
2
[LLVMdev] MIPS n64 ABI and non-PIC
...> add $1, $1, %higher(foo)
>
> dsll $1, $1, 32
>
> lui $2, %hi(foo)
>
> add $2, $2, %lo(foo)
>
> add $1, $1, $2
>
> which is 6 instructions per-symbol referenced. The current PIC
> implementation generates this:
>
> lui $1, %hi(%neg(%gp_rel(bar)))
>
> daddu $1, $1, $25
>
> daddiu $1, $1, %lo(%neg(%gp_rel(bar)))
>
> ld $2, %got_disp(foo)($1)
>
> which is a one-time cost of 3 instructions to set up the GOT pointer, plus
> one load per-symbol referenced.
>
>
>
> *From:* llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounc...
2018 Sep 06
2
How to add Loongson ISA for Mips target?
...000000,-8
>> .fmask 0x00000000,0
>> .set noreorder
>> .set nomacro
>> daddiu $sp,$sp,-48
>> gssq $31,$fp,32($sp)
>> sd $28,24($sp)
>> move $fp,$sp
>> lui $28,%hi(%neg(%gp_rel(main)))
>> daddu $28,$28,$25
>> daddiu $28,$28,%lo(%neg(%gp_rel(main)))
>> move $2,$4
>> sd $5,8($fp)
>> sll $2,$2,0
>> sw $2,0($fp)
>> ld $2,%got_page(.LC0)($28)
>> daddiu $4,$2,%got_ofst(.LC0)
>> ld $2,%call...