search for: d880

Hi All, I've been testing reliability with t.38 faxing pass through with * 1.4.21.1, Linksys ATA's 2102 x 2, Sharp UX-B800SE and Cannon ImageClass D880. cannon> <2102 #1> <SIP> <*> <SIP> <2102 #2> <sharp Started out with default settings on all devices, configured Asterisk to handle T.38 pass through, the configuration I believe is solid. I get relaiable results faxing from the sharp to the cannon. I get int...

...e 330b Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 74 Region 0: I/O ports at d880 [size=8] Region 1: I/O ports at d800 [size=4] Region 2: I/O ports at d480 [size=8] Region 3: I/O ports at d400 [size=4] Region 4: I/O ports at d080 [size=32] Region 5: Memory at faffc000 (32-bit, non-prefetchable) [size=2K] Capabilities: [80] MSI: Enable+ Count=1/16 Maskable- 64bit- Address...

...stub fixme:ntdll:NtQuerySystemInformation (0x0000002d,0xf3e95c,0x00000020,0xf3f5ec) stub fixme:ntdll:NtQuerySystemInformation (0x00000017,0xf3e95c,0x00000b30,0xf3f5ec) stub fixme:msvcrt:_set_error_mode dummy implementation (old mode: 2, new mode: 2) fixme:setupapi:SetupDiGetClassDevsA {00f3fb18-d880-0056-786d-5a00ffffffff} (null) (nil) 00000012 fixme:setupapi:SetupDiDestroyDeviceInfoList ffffffff fixme:setupapi:SetupDiGetClassDevsA {00000004-f7b4-00f3-0200-0000b8f8f300} (null) (nil) 00000012 fixme:bitblt:X11DRV_BitBlt potential optimization - client-side DIB copy

...> Kernel driver in use: pcieport Kernel modules: shpchp 09:00.0 SATA controller: Device 1b4b:9123 (rev 10) (prog-if 01 [AHCI 1.0]) Subsystem: ASUSTeK Computer Inc. Device 8400 Flags: bus master, fast devsel, latency 0, IRQ 55 I/O ports at dc00 [size=8] I/O ports at d880 [size=4] I/O ports at d800 [size=8] I/O ports at d480 [size=4] I/O ports at d400 [size=16] Memory at f7dff000 (32-bit, non-prefetchable) [size=2K] Expansion ROM at f7de0000 [disabled] [size=64K] Capabilities: [40] Power Management version 3 Capabilities: [50] MSI:...

...t >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 32 Region 0: Memory at fbd60000 (32-bit, non-prefetchable) [size=128K] Region 1: Memory at fbd40000 (32-bit, non-prefetchable) [size=128K] Region 2: I/O ports at d880 [size=32] Region 3: Memory at fbdb8000 (32-bit, non-prefetchable) [size=16K] Expansion ROM at fbd20000 [disabled] [size=128K] Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=1 PME-...

Hey hope this opne is a "make senser". Has anyone tried the "Subject line" combo?, I''ve compiled a dozen src.rpm kernel 3.0 and 3.1 packages with no luck to try native upstream Dom0 kernel support with no success, just a kernel oops and constant reboots. I followed Fedora''s wiki on building a custom kernel, even used F16''s .config which also was a

Hey hope this opne is a "make senser". Has anyone tried the "Subject line" combo?, I''ve compiled a dozen src.rpm kernel 3.0 and 3.1 packages with no luck to try native upstream Dom0 kernel support with no success, just a kernel oops and constant reboots. I followed Fedora''s wiki on building a custom kernel, even used F16''s .config which also was a

Now that x86-64 has directly accessible percpu variables, it can also implement the direct versions of these operations, which operate on a vcpu_info structure directly embedded in the percpu area. In fact, the 64-bit versions are more or less identical, and so can be shared. The only two differences are: 1. xen_restore_fl_direct takes its argument in eax on 32-bit, and rdi on 64-bit.

...:08.0 0101: 10de:03f6 (rev a2) (prog-if 85) Subsystem: 1849:03f6 Flags: bus master, 66MHz, fast devsel, latency 0, IRQ 225 I/O ports at 0e00 [size=8] I/O ports at 0e20 [size=4] I/O ports at 0e40 [size=8] I/O ports at 0e60 [size=4] I/O ports at d880 [size=16] Memory at dfffc000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Capabilities: [b0] Message Signalled Interrupts: 64bit+ Queue=0/2 Enable- Capabilities: [cc] HyperTransport: MSI Mapping 00:09.0 0604: 10de:03e8 (rev a2)...

...:08.0 0101: 10de:03f6 (rev a2) (prog-if 85) Subsystem: 1849:03f6 Flags: bus master, 66MHz, fast devsel, latency 0, IRQ 225 I/O ports at 0e00 [size=8] I/O ports at 0e20 [size=4] I/O ports at 0e40 [size=8] I/O ports at 0e60 [size=4] I/O ports at d880 [size=16] Memory at dfffc000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Capabilities: [b0] Message Signalled Interrupts: 64bit+ Queue=0/2 Enable- Capabilities: [cc] HyperTransport: MSI Mapping 00:09.0 0604: 10de:03e8 (rev a2)...